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authorHannah Williams <hannah.williams@intel.com>2017-12-13 12:44:26 -0800
committerAaron Durbin <adurbin@chromium.org>2018-02-05 18:53:16 +0000
commit1177bf516540b62e54cefdf346bb6e8a7c376642 (patch)
tree16816da12ba7ba556300e8a5599b0bb21f1a631c /src/soc/rockchip
parent8b40b675a8e45f748e7fbf2495a7f01684fa0401 (diff)
soc/intel/common/block/pmc: Fix ACPI BAR and PCI_COMMAND in PMC config space
read_resources in common/block/pmc/pmc.c is corrupting the BAR at offset 0x20. pch_pmc_read_resources | pci_dev_read_resources | pci_get_resource Within pci_get_resource, the BAR is read and written back. Since read of ACPI BAR does not return the correct value, the subsequent write corrupts the BAR. Hence re-programming the BAR. Also, reading PMC STATUSCOMMAND register does not return bit 0 correctly in pci_dev_enable_resources. This causes IO SPACE ACCESS to get disabled. Hence making sure IO ACCESS gets enabled by setting dev->command TEST=Can boot to OS Without this change coreboot will be stuck at "Disabling ACPI via APMC:" Change-Id: I27062419d06127951ecbbb641835d06ca39ff435 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/23230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
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