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authorDavid Hendricks <dhendrix@chromium.org>2014-09-29 13:37:51 -0700
committerAaron Durbin <adurbin@google.com>2015-04-02 23:27:36 +0200
commit3b631615f6c382965e239704b1f417c6a67b6730 (patch)
tree7bceee3330a2667b489388f2e5c8b37416215344 /src/soc/rockchip
parent7e9ffbcc826025fd6501feb700a9ff2b83bcd966 (diff)
pinky: Move some init to mainboard bootblock
This patch moves init for I2C, SPI, ChromeOS GPIOs to the board-specific bootblock init function on Pinky, the idea being to isolate SoC code so that it's more readily adaptable for different boards. BUG=none BRANCH=none TEST=built and booted on Pinky Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I75516bbd332915c1f61249844e18415b4e23c520 Original-Reviewed-on: https://chromium-review.googlesource.com/220410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> (cherry picked from commit 0a7dec2fe70679c3457b0bfc7138b4a90b6217c8) Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ib2c2e00b11c294a8d5bdd07a2cd59503179f0a84 Reviewed-on: http://review.coreboot.org/9243 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/rk3288/bootblock.c36
1 files changed, 15 insertions, 21 deletions
diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c
index d7bc67a38d..eec3456613 100644
--- a/src/soc/rockchip/rk3288/bootblock.c
+++ b/src/soc/rockchip/rk3288/bootblock.c
@@ -17,34 +17,28 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#include <console/console.h>
-#include <arch/cache.h>
#include <arch/io.h>
#include <bootblock_common.h>
+#include <console/console.h>
+#include <soc/rockchip/rk3288/grf.h>
+#include "addressmap.h"
#include "timer.h"
#include "clock.h"
-#include "grf.h"
-#include "spi.h"
-#include <vendorcode/google/chromeos/chromeos.h>
-#include <soc/rockchip/rk3288/i2c.h>
static void bootblock_cpu_init(void)
{
- writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
- writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
- writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
- /*i2c1 for tpm*/
- writel(IOMUX_I2C1, &rk3288_grf->iomux_i2c1);
-
- /* spi0 for chrome ec */
- writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rk3288_init_timer();
- console_init();
- rkclk_init();
- /*i2c1 for tpm 400khz*/
- i2c_init(1, 400000);
- rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS);
- rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
- setup_chromeos_gpios();
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) {
+ switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) {
+ case UART2_BASE:
+ writel(IOMUX_UART2, &rk3288_grf->iomux_uart2);
+ break;
+ default:
+ die("TODO: Handle setup for console UART if needed");
+ }
+ console_init();
+ }
+
+ rkclk_init();
}