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authorDerek Basehore <dbasehore@chromium.org>2016-06-22 16:42:30 -0700
committerMartin Roth <martinroth@google.com>2016-07-12 00:26:54 +0200
commit9e624fc27f123c8b5eb6ef5a1ecd57facca16a7f (patch)
tree52a8106d8cda9a43b3dde90b4903b8c9e6eac04c /src/soc/rockchip
parent58826fc85e63dde8f5171dfb37224bb1b7ceb9b2 (diff)
rockchip/rk3399: Clean up comments in sdram.c
Cleans up the comments in sdram.c to make them consistent. BRANCH=none BUG=none TEST=make sure gru/kevin build and boot also, run "stressapptest -M 1024 -s 3600" to make sure it passes Change-Id: I1daf72b847374d549389bacd2fa0a9f8f231b190 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 63a224d6f4b0e4d13bc372c05c4b9196895d553f Original-Change-Id: Iaf8a32cfe2b22c4ccff71952f90d162ad8c2d3e7 Original-Signed-off-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355665 Original-Reviewed-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/15579 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/rk3399/sdram.c65
1 files changed, 36 insertions, 29 deletions
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index 4ad7b0e00a..f56ac175ce 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -119,8 +119,7 @@ static void phy_dll_bypass_set(u32 channel,
struct rk3399_ddr_publ_regs *ddr_publ_regs, u32 freq)
{
if (freq <= 125*MHz) {
- /* phy_sw_master_mode_X */
- /* PHY_86/214/342/470 4bits offset_8 */
+ /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
setbits_le32(&ddr_publ_regs->denali_phy[86],
(0x3 << 2) << 8);
setbits_le32(&ddr_publ_regs->denali_phy[214],
@@ -130,8 +129,7 @@ static void phy_dll_bypass_set(u32 channel,
setbits_le32(&ddr_publ_regs->denali_phy[470],
(0x3 << 2) << 8);
- /* phy_adrctl_sw_master_mode */
- /* PHY_547/675/803 4bits offset_16 */
+ /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
setbits_le32(&ddr_publ_regs->denali_phy[547],
(0x3 << 2) << 16);
setbits_le32(&ddr_publ_regs->denali_phy[675],
@@ -139,8 +137,7 @@ static void phy_dll_bypass_set(u32 channel,
setbits_le32(&ddr_publ_regs->denali_phy[803],
(0x3 << 2) << 16);
} else {
- /* phy_sw_master_mode_X */
- /* PHY_86/214/342/470 4bits offset_8 */
+ /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
clrbits_le32(&ddr_publ_regs->denali_phy[86],
(0x3 << 2) << 8);
clrbits_le32(&ddr_publ_regs->denali_phy[214],
@@ -150,8 +147,7 @@ static void phy_dll_bypass_set(u32 channel,
clrbits_le32(&ddr_publ_regs->denali_phy[470],
(0x3 << 2) << 8);
- /* phy_adrctl_sw_master_mode */
- /* PHY_547/675/803 4bits offset_16 */
+ /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
clrbits_le32(&ddr_publ_regs->denali_phy[547],
(0x3 << 2) << 16);
clrbits_le32(&ddr_publ_regs->denali_phy[675],
@@ -274,7 +270,7 @@ static void set_ds_odt(u32 channel,
clrsetbits_le32(&ddr_publ_regs->denali_phy[672], 0xff, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[800], 0xff, reg_value);
- /* phy_pad_addr_drive 29bits DENALI_PHY_928 offset_0 */
+ /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
clrsetbits_le32((&ddr_publ_regs->denali_phy[928]), 0xff, reg_value);
/* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
@@ -329,6 +325,7 @@ static void set_ds_odt(u32 channel,
clrsetbits_le32(&ddr_publ_regs->denali_phy[936], 0x1 << 17, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[940], 0x1 << 17, reg_value);
clrsetbits_le32(&ddr_publ_regs->denali_phy[934], 0x1 << 17, reg_value);
+
/* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
clrsetbits_le32(&ddr_publ_regs->denali_phy[930], 0x1 << 17, reg_value);
}
@@ -368,13 +365,11 @@ static void phy_io_config(u32 channel,
clrsetbits_le32(&ddr_publ_regs->denali_phy[915], 0xfff << 16,
reg_value << 16);
- /* mode setting */
if (sdram_params->dramtype == LPDDR4)
mode_sel = 0x6;
else if (sdram_params->dramtype == LPDDR3)
mode_sel = 0x0;
else if (sdram_params->dramtype == DDR3)
- /* DDR3L */
mode_sel = 0x1;
/* PHY_924 PHY_PAD_FDBK_DRIVE */
@@ -402,7 +397,6 @@ static void phy_io_config(u32 channel,
clrsetbits_le32(&ddr_publ_regs->denali_phy[939], 0x7 << 14,
mode_sel << 14);
- /* SPEED */
if (sdram_params->ddr_freq < 400 * MHz)
speed = 0x0;
else if (sdram_params->ddr_freq < 800 * MHz)
@@ -448,7 +442,8 @@ static void pctl_cfg(u32 channel,
u32 tmp, tmp1, tmp2;
u32 pwrup_srefresh_exit;
- /* workaround controller bug:
+ /*
+ * work around controller bug:
* Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
*/
copy_to_reg(&ddr_pctl_regs->denali_ctl[1],
@@ -528,8 +523,10 @@ static void pctl_cfg(u32 channel,
clrsetbits_le32(&ddr_publ_regs->denali_phy[468],
0xff << 8, (tmp + 0x10) << 8);
- /* phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8 */
- /* dq_tsel_wr_end[7:4] add Half cycle */
+ /*
+ * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_83/211/339/467 offset_8
+ * dq_tsel_wr_end[7:4] add Half cycle
+ */
tmp = (read32(&ddr_publ_regs->denali_phy[83]) >> 16) & 0xff;
clrsetbits_le32(&ddr_publ_regs->denali_phy[83],
0xff << 16, (tmp + 0x10) << 16);
@@ -549,7 +546,8 @@ static void pctl_cfg(u32 channel,
clrsetbits_le32(&ddr_publ_regs->denali_phy[957],
0x3 << 24, 0x2 << 24);
- /* FIXME:
+ /*
+ * FIXME:
* need to care ERROR bit
*/
while (!(read32(&ddr_pctl_regs->denali_ctl[203]) & (1 << 3)))
@@ -563,11 +561,12 @@ static void select_per_cs_training_index(u32 channel, u32 rank)
{
struct rk3399_ddr_publ_regs *ddr_publ_regs = rk3399_ddr_publ[channel];
- /*PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16*/
+ /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
if ((read32(&ddr_publ_regs->denali_phy[84])>>16) & 1) {
- /*PHY_8/136/264/392
- *phy_per_cs_training_index_X 1bit offset_24
- */
+ /*
+ * PHY_8/136/264/392
+ * phy_per_cs_training_index_X 1bit offset_24
+ */
clrsetbits_le32(&ddr_publ_regs->denali_phy[8],
0x1 << 24, rank << 24);
clrsetbits_le32(&ddr_publ_regs->denali_phy[136],
@@ -738,8 +737,10 @@ static int data_training(u32 channel,
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
- /* check status obs */
- /* PHY_532/660/789 phy_adr_calvl_obs1_:0:32 */
+ /*
+ * check status obs
+ * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
+ */
obs_0 = read32(&ddr_publ_regs->denali_phy[532]);
obs_1 = read32(&ddr_publ_regs->denali_phy[660]);
obs_2 = read32(&ddr_publ_regs->denali_phy[789]);
@@ -775,7 +776,7 @@ static int data_training(u32 channel,
select_per_cs_training_index(channel, i);
while (1) {
- /*PI_174 PI_INT_STATUS:RD:8:18*/
+ /* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
/*
@@ -816,8 +817,10 @@ static int data_training(u32 channel,
clrsetbits_le32(&ddr_pi_regs->denali_pi[80],
0x3 << 24,
0x2 << 24);
- /* PI_74 PI_RDLVL_GATE_REQ:WR:16:1 */
- /* PI_RDLVL_CS:RW:24:2 */
+ /*
+ * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
+ * PI_RDLVL_CS:RW:24:2
+ */
clrsetbits_le32(&ddr_pi_regs->denali_pi[74],
(0x1 << 16) | (0x3 << 24),
(0x1 << 16) | (i << 24));
@@ -826,7 +829,8 @@ static int data_training(u32 channel,
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
- /* check status obs
+ /*
+ * check status obs
* PHY_43/171/299/427
* PHY_GTLVL_STATUS_OBS_x:16:8
*/
@@ -869,7 +873,8 @@ static int data_training(u32 channel,
while (1) {
/* PI_174 PI_INT_STATUS:RD:8:18 */
tmp = read32(&ddr_pi_regs->denali_pi[174]) >> 8;
- /* make sure status obs not report error bit
+ /*
+ * make sure status obs not report error bit
* PHY_46/174/302/430
* phy_rdlvl_status_obs_X:16:8
*/
@@ -888,8 +893,10 @@ static int data_training(u32 channel,
/* wdq leveling(LPDDR4 support) */
if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
for (i = 0; i < rank; i++) {
- /* disable PI_WDQLVL_VREF_EN before wdq leveling? */
- /* PI_181 PI_WDQLVL_VREF_EN:RW:8:1 */
+ /*
+ * disable PI_WDQLVL_VREF_EN before wdq leveling?
+ * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
+ */
clrbits_le32(&ddr_pi_regs->denali_pi[181], 0x1 << 8);
/* PI_124 PI_WDQLVL_EN:RW:16:2 */
clrsetbits_le32(&ddr_pi_regs->denali_pi[124],
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-24 19:04:05 +0000