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authorPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-11-26 15:04:46 +0100
committerPhilipp Deppenwiese <zaolin.daisuki@gmail.com>2018-11-30 10:26:56 +0000
commit2af17af82981df83b91a58f88dc6aa143e6dee55 (patch)
tree355a591acfc032b99a272427523ef073b2abafcb /src/soc/rockchip
parentaea00f496b1cf41fd5b568b4c6079c2ab76eafd4 (diff)
security/vboot: Fix remaining measured boot issues
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip')
-rw-r--r--src/soc/rockchip/rk3288/include/soc/memlayout.ld6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
index fc3758b1fa..6320fadcba 100644
--- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld
@@ -31,9 +31,9 @@ SECTIONS
SRAM_START(0xFF700000)
TTB(0xFF700000, 16K)
BOOTBLOCK(0xFF704004, 20K - 4)
- PRERAM_CBMEM_CONSOLE(0xFF709000, 3K)
- VBOOT2_WORK(0xFF709C00, 12K)
- OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K)
+ PRERAM_CBMEM_CONSOLE(0xFF709000, 2K)
+ VBOOT2_WORK(0xFF709800, 12K)
+ OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K)
PRERAM_CBFS_CACHE(0xFF717000, 1K)
TIMESTAMP(0xFF717400, 0x180)
STACK(0xFF717580, 3K - 0x180)