diff options
| author | Nickey Yang <nickey.yang@rock-chips.com> | 2017-05-25 11:23:23 +0800 |
|---|---|---|
| committer | Julius Werner <jwerner@chromium.org> | 2017-05-26 23:47:17 +0200 |
| commit | 5be0b2e03d7550468b7ee495baebe1123ccdda77 (patch) | |
| tree | 879dc00b8246cd563d2bc790227bab4d4364f79f /src/soc/rockchip/rk3399 | |
| parent | 6b697ef207674c58b47058b37e11fc97634d5cb4 (diff) | |
rockchip/rk3399: fix rk_mipi_dsi_phy_init err
This patch fix rk_mipi_dsi_phy_init error return.
Change-Id: Ie260975ad6ed26c37aa8bb65dfcef4db2407a2da
Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399')
| -rw-r--r-- | src/soc/rockchip/rk3399/mipi.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 5c8f4c2e33..9491b91d7f 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -95,7 +95,7 @@ static void rk_mipi_dsi_phy_write(struct rk_mipi_dsi *dsi, static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi) { - int ret, testdin, vco; + int testdin, vco; int lane_mbps = div_round_up(dsi->lane_bps, USECS_PER_SEC); vco = (lane_mbps < 200) ? 0 : (lane_mbps + 100) / 200; @@ -156,7 +156,7 @@ static int rk_mipi_dsi_phy_init(struct rk_mipi_dsi *dsi) write32(&mipi_regs->dsi_phy_rstz, PHY_ENFORCEPLL | PHY_ENABLECLK | PHY_UNRSTZ | PHY_UNSHUTDOWNZ); - return ret; + return 0; } static inline int mipi_dsi_pixel_format_to_bpp(enum mipi_dsi_pixel_format fmt) @@ -421,7 +421,8 @@ void rk_mipi_prepare(const struct edid *edid, u32 display_on_mdelay, u32 video_m rk_mipi_dsi_dphy_timing_config(&rk_mipi); rk_mipi_dsi_dphy_interface_config(&rk_mipi); rk_mipi_dsi_clear_err(&rk_mipi); - rk_mipi_dsi_phy_init(&rk_mipi); + if (rk_mipi_dsi_phy_init(&rk_mipi) < 0) + return; rk_mipi_dsi_wait_for_two_frames(&rk_mipi, edid); rk_mipi_dsi_set_mode(&rk_mipi, MIPI_DSI_CMD_MODE); |