diff options
| author | Furquan Shaikh <furquan@chromium.org> | 2017-05-19 10:54:30 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-05-22 18:47:32 +0200 |
| commit | 7941c96f8eaeb35179b30283ef7bfab6929f2bb7 (patch) | |
| tree | a4511a4f53c73346298c06944bcb9a596d72442e /src/soc/rockchip/rk3399/saradc.c | |
| parent | 75ef6ec29e7c8f65df96cba0c197580f0d3e9ece (diff) | |
soc/intel/skylake: Add entry for deep Sx wake
If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.
BUG=b:38436041
TEST=Verified that elog entries are updated correctly:
Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode
Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0
Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0
Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/saradc.c')
0 files changed, 0 insertions, 0 deletions