diff options
| author | Furquan Shaikh <furquan@google.com> | 2020-06-11 11:59:07 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2020-06-13 06:49:23 +0000 |
| commit | 46514c2b877c29c2d7c2061a9785736e270c0c62 (patch) | |
| tree | 2f78550192bce548139ef49fdac6623dad578703 /src/soc/rockchip/rk3399/memlayout.ld | |
| parent | 00148bba7146318e2e815d8c13e33278f63814c9 (diff) | |
treewide: Add Kconfig variable MEMLAYOUT_LD_FILE
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/memlayout.ld')
| -rw-r--r-- | src/soc/rockchip/rk3399/memlayout.ld | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld new file mode 100644 index 0000000000..72836b5130 --- /dev/null +++ b/src/soc/rockchip/rk3399/memlayout.ld @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <memlayout.h> +#include <arch/header.ld> + +SECTIONS +{ + DRAM_START(0x00000000) + BL31(0, 0x100000) + POSTRAM_CBFS_CACHE(0x00100000, 8M) + RAMSTAGE(0x00900000, 2M) + DMA_COHERENT(0x10000000, 2M) + + /* 8K of special SRAM in PMU power domain. */ + SYMBOL(pmu_sram, 0xFF3B0000) + WATCHDOG_TOMBSTONE(0xFF3B1FFC, 4) + SYMBOL(epmu_sram, 0xFF3B2000) + + SRAM_START(0xFF8C0000) +#if ENV_RAMSTAGE + REGION(bl31_sram, 0xFF8C0000, 64K, 1) +#else + PRERAM_CBFS_CACHE(0xFF8C0000, 5K) + FMAP_CACHE(0xFF8C1400, 2K) + TIMESTAMP(0xFF8C1C00, 1K) + /* 0xFF8C2004 is the entry point address the masked ROM will jump to. */ + OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4) + BOOTBLOCK(0xFF8D8000, 40K) +#endif + VBOOT2_WORK(0XFF8E2000, 12K) + TTB(0xFF8E5000, 24K) + PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K) + STACK(0xFF8ED000, 12K) + SRAM_END(0xFF8F0000) +} |