diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-09-15 22:59:55 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-11-02 17:29:48 +0100 |
| commit | 883f5cbdcea6e8e4dbca57ff0a430338c9159ed2 (patch) | |
| tree | 5fb86a9b3dcc8537c240c81ebafd275897fe9948 /src/soc/rockchip/rk3399/include | |
| parent | 84164603188175abd2a3d8eeab1adc5efc33330f (diff) | |
rockchip/rk3399: sdram: also prepare the index1 configuration
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to
train alternative configurations first, so do the training and store the
values.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I944a4b297a4ed6966893aa09553da88171307a42
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2
Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386596
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17104
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/addressmap.h | 2 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/sdram.h | 12 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index d316c3805d..1762a8d277 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -17,7 +17,6 @@ #define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ #define MAX_DRAM_ADDRESS 0xF8000000 - #define PMUGRF_BASE 0xff320000 #define PMUSGRF_BASE 0xff330000 #define PMUCRU_BASE 0xff750000 @@ -69,6 +68,7 @@ #define SERVER_MSCH0_BASE_ADDR 0xffa84000 #define DDRC1_BASE_ADDR 0xffa88000 #define SERVER_MSCH1_BASE_ADDR 0xffa8c000 +#define CIC_BASE_ADDR 0xff620000 #define USB_OTG0_DWC3_BASE 0xfe80c100 #define USB_OTG1_DWC3_BASE 0xfe90c100 diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 1ec6d3958c..bf99b35f36 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -127,6 +127,18 @@ struct rk3399_msch_timings { u32 agingx0; }; +struct rk3399_ddr_cic_regs { + u32 cic_ctrl0; + u32 cic_ctrl1; + u32 cic_idle_th; + u32 cic_cg_wait_th; + u32 cic_status0; + u32 cic_status1; + u32 cic_ctrl2; + u32 cic_ctrl3; + u32 cic_ctrl4; +}; + /* DENALI_CTL_00 */ #define START (1) |