rockchip: rk3399: initialize display for eDP

This patch adds functions to init the display. To set up the display,
initialize the eDP and read the EDID.  Based on these, we then
set the clock for VOP, and finally enable VOP and backlight.

For a mainboard, it should set the vop_id, vop_mode and
framebuffer_bits_per_pixel in devicetree.cb.

For VOP_MODE_AUTO_DETECT, it will try eDP first and then
HDMI (which is not supported yet).

EDIT: Updated Makefile to only build in new files if
MAINBOARD_DO_NATIVE_VGA_INIT is enabled. All of these
platforms should have it enabled, so this shouldn't make
any difference except now, before the platform code is
in place.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=test with the other patch

Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: c1020cc806775629f4d5dc57bd805a9a12169386
Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342336
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14857
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

3 files changed, 31 insertions, 0 deletions

diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index 28cbd7a56e..77fca9e6f7 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -59,6 +59,11 @@
 #define TSADC_BASE		0xff260000
 #define SARADC_BASE		0xff100000
 #define RK_PWM_BASE		0xff420000
+#define EDP_BASE		0xff970000
+
+#define VOP_BIG_BASE		0xff900000 /* corresponds to vop_id 0 */
+#define VOP_LIT_BASE		0xff8f0000 /* corresponds to vop_id 1 */
+
 
 #define DDRC0_BASE_ADDR		0xffa80000
 #define SERVER_MSCH0_BASE_ADDR	0xffa84000
diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h
new file mode 100644
index 0000000000..7ccde5611a
--- /dev/null
+++ b/src/soc/rockchip/rk3399/include/soc/display.h
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3399_DISPLAY_H__
+#define __SOC_ROCKCHIP_RK3399_DISPLAY_H__
+
+#define REF_CLK_24M (0x1 << 0)
+
+void rk_display_init(device_t dev, uintptr_t lcdbase,
+		     unsigned long fb_size);
+void mainboard_power_on_backlight(void);
+
+#endif
diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
index edb246d6f0..ac16394c86 100644
--- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld
+++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld
@@ -22,6 +22,7 @@ SECTIONS
 	POSTRAM_CBFS_CACHE(0x00100000, 1M)
 	RAMSTAGE(0x00300000, 256K)
 	DMA_COHERENT(0x10000000, 2M)
+	FRAMEBUFFER(0x10200000, 8M)
 
 	SRAM_START(0xFF8C0000)
 	BOOTBLOCK(0xFF8C2004, 32K - 4)