diff options
| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-05-06 16:50:48 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-18 20:19:29 +0200 |
| commit | f4181ce3b312b2113010403feb40fd3d179acad1 (patch) | |
| tree | 410d846b47e014793fb2fe2747c9bdf29bb10942 /src/soc/rockchip/rk3399/include | |
| parent | 307ca379d147d3ecce4d05a2172f20a6f14950a2 (diff) | |
rockchip: rk3399: add tsadc driver
This patch configures clock for tsadc and then
makes it in automatic mode to generate TSHUT when
CPU temperature is higer than 120 degree Celsius.
BRANCH=none
BUG=chrome-os-partner:52382,chrome-os-partner:51537
TEST=Set a lower tshut threshold(45C), run coreboot and check
that coreboot reboot again and again.
Change-Id: I0b070a059d2941f12d31fc3002e78ea083e70b13
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 05107bd6a3430e31db216c247ff0213e12373390
Original-Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342797
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/14848
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/include')
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/clock.h | 1 | ||||
| -rw-r--r-- | src/soc/rockchip/rk3399/include/soc/tsadc.h | 26 |
2 files changed, 27 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 65e2e74a57..3b60d547cf 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -108,6 +108,7 @@ void rkclk_configure_cpu(enum apll_l_frequencies apll_l_freq); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_saradc(unsigned int hz); void rkclk_configure_spi(unsigned int bus, unsigned int hz); +void rkclk_configure_tsadc(unsigned int hz); void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz); void rkclk_ddr_reset(u32 ch, u32 ctl, u32 phy); uint32_t rkclk_i2c_clock_for_bus(unsigned bus); diff --git a/src/soc/rockchip/rk3399/include/soc/tsadc.h b/src/soc/rockchip/rk3399/include/soc/tsadc.h new file mode 100644 index 0000000000..b1f617df75 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/tsadc.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_TSADC_H__ +#define __SOC_ROCKCHIP_RK3399_TSADC_H__ + +enum { + TSHUT_POL_HIGH = 1 << 8, + TSHUT_POL_LOW = 0 << 8 +}; + +void tsadc_init(uint32_t polarity); + +#endif |