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authorSubrata Banik <subrata.banik@intel.com>2017-08-14 13:23:54 +0530
committerMartin Roth <martinroth@google.com>2017-08-21 16:22:51 +0000
commitce4c9ec4f61cfba8a25adf74ad40d582859ea8b8 (patch)
treebfc73bac415c8375bd97ecfdf4d472fe2a6563c0 /src/soc/rockchip/rk3399/display.c
parent19a7adeffe5a9d50fec9cb4ab81a7d40ce387f08 (diff)
soc/intel/cannonlake: Add Kconfig option to select UART index
Cannonlake SOC has two possible ways to make serial console functional. 1. Legacy IO based access using Port 0x3F8. 2. LPSS UART PCI based access. This patch to provide option to select index for LPSS UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 PCI based LPSS UART2 is by default enabled for Chrome Design. Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/20998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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