diff options
| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-05-06 16:50:48 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-18 20:19:29 +0200 |
| commit | f4181ce3b312b2113010403feb40fd3d179acad1 (patch) | |
| tree | 410d846b47e014793fb2fe2747c9bdf29bb10942 /src/soc/rockchip/rk3399/clock.c | |
| parent | 307ca379d147d3ecce4d05a2172f20a6f14950a2 (diff) | |
rockchip: rk3399: add tsadc driver
This patch configures clock for tsadc and then
makes it in automatic mode to generate TSHUT when
CPU temperature is higer than 120 degree Celsius.
BRANCH=none
BUG=chrome-os-partner:52382,chrome-os-partner:51537
TEST=Set a lower tshut threshold(45C), run coreboot and check
that coreboot reboot again and again.
Change-Id: I0b070a059d2941f12d31fc3002e78ea083e70b13
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 05107bd6a3430e31db216c247ff0213e12373390
Original-Change-Id: Iffe54d3b09080d0f1ff31e8b3020d69510f07c95
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342797
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/14848
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 46c7a39006..53c6e30e5b 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -159,6 +159,13 @@ enum { CLK_SARADC_DIV_CON_MASK = 0xff, CLK_SARADC_DIV_CON_SHIFT = 8, + /* CLKSEL_CON27 */ + CLK_TSADC_SEL_X24M = 0x0, + CLK_TSADC_SEL_MASK = 1, + CLK_TSADC_SEL_SHIFT = 15, + CLK_TSADC_DIV_CON_MASK = 0x3ff, + CLK_TSADC_DIV_CON_SHIFT = 0, + /* CLKSEL_CON47 & CLKSEL_CON48 */ ACLK_VOP_PLL_SEL_MASK = 0x3, ACLK_VOP_PLL_SEL_SHIFT = 6, @@ -714,3 +721,18 @@ int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz) return 0; } + +void rkclk_configure_tsadc(unsigned int hz) +{ + int src_clk_div; + + /* use 24M as src clock */ + src_clk_div = OSC_HZ / hz; + assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ)); + + write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( + CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | + CLK_TSADC_SEL_MASK << CLK_TSADC_SEL_SHIFT, + src_clk_div << CLK_TSADC_DIV_CON_SHIFT | + CLK_TSADC_SEL_X24M << CLK_TSADC_SEL_SHIFT)); +} |