diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-05-19 11:39:20 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-08 23:27:01 +0200 |
| commit | 96fbc31027b8e208c264d96c04f45799cea3417e (patch) | |
| tree | 2f95d8ee6e932f621943347c3ec05696545d4620 /src/soc/rockchip/rk3399/clock.c | |
| parent | 8f8cf4d3369ef9d4391dc96215832aad1f5fda67 (diff) | |
rockchip: rk3399: Add support i2s
This patch enable and configure the clocks and IOMUX for i2s audio path,
and the i2s0 clock is from CPLL.
Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155
for the i2s clock div and gate setting.
BRANCH=none
BUG=chrome-os-partner:52172
TEST=boot kevin rev1, press ctrl+u and hear the beep voice.
Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 9c58fa7
Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68
Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/347526
Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/15034
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index ba66230e23..6d40cd2578 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -686,6 +686,50 @@ uint32_t rkclk_i2c_clock_for_bus(unsigned bus) return freq; } +static u32 clk_gcd(u32 a, u32 b) +{ + while (b != 0) { + int r = b; + b = a % b; + a = r; + } + return a; +} + +void rkclk_configure_i2s(unsigned int hz) +{ + int n, d; + int v; + + /** + * clk_i2s0_sel: divider ouput from fraction + * clk_i2s0_pll_sel source clock: cpll + * clk_i2s0_div_con: 1 (div+1) + */ + write32(&cru_ptr->clksel_con[28], + RK_CLRSETBITS(3 << 8 | 1 << 7 | 0x7f << 0, + 1 << 8 | 0 << 7 | 0 << 0)); + + /* make sure and enable i2s0 path gates */ + write32(&cru_ptr->clkgate_con[8], + RK_CLRBITS(1 << 12 | 1 << 5 | 1 << 4 | 1 << 3)); + + /* set frac divider */ + v = clk_gcd(CPLL_HZ, hz); + n = (CPLL_HZ / v) & (0xffff); + d = (hz / v) & (0xffff); + assert(hz == CPLL_HZ / n * d); + write32(&cru_ptr->clksel_con[96], d << 16 | n); + + /** + * clk_i2sout_sel clk_i2s + * clk_i2s_ch_sel: clk_i2s0 + */ + write32(&cru_ptr->clksel_con[31], + RK_CLRSETBITS(1 << 2 | 3 << 0, + 0 << 2 | 0 << 0)); +} + void rkclk_configure_saradc(unsigned int hz) { int src_clk_div; |