diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-26 22:53:49 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-11-29 12:17:45 +0000 |
| commit | 6df3b64c77a868ab8526b980561ed2be3fe392b6 (patch) | |
| tree | a95ac78c1e4e222971ee9749e9e114494681e9c4 /src/soc/rockchip/rk3399/clock.c | |
| parent | 1a5ce95815210032783d01e830390ee5b6a54dc5 (diff) | |
src: Remove duplicated round up function
This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 0b8c83f90e..cce1d69ee6 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -429,10 +429,10 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div) return -1; } - postdiv1 = div_round_up(VCO_MIN_KHZ, freq_khz); + postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); if (postdiv1 > max_postdiv1) { - postdiv2 = div_round_up(postdiv1, max_postdiv1); - postdiv1 = div_round_up(postdiv1, postdiv2); + postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); + postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); } vco_khz = freq_khz * postdiv1 * postdiv2; @@ -605,9 +605,9 @@ void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster) apll_hz = apll_cfgs[freq]->freq; rkclk_set_pll(pll_con, apll_cfgs[freq]); - aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1; - pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1; - atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1; + aclkm_div = DIV_ROUND_UP(apll_hz, ACLKM_CORE_HZ) - 1; + pclk_dbg_div = DIV_ROUND_UP(apll_hz, PCLK_DBG_HZ) - 1; + atclk_div = DIV_ROUND_UP(apll_hz, ATCLK_CORE_HZ) - 1; write32(&cru_ptr->clksel_con[con_base], RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << |