diff options
| author | Martin Roth <martinroth@google.com> | 2018-05-20 17:46:51 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-05-22 02:54:24 +0000 |
| commit | 9641a92b112c5759ccb956287e80ba4a4983611b (patch) | |
| tree | efe2c9f7aae0756afd26600cbb584afde6c25f31 /src/soc/rockchip/rk3399/clock.c | |
| parent | 8f25a6680e23663f4c88f7fe61a7a62e8fe284c4 (diff) | |
src: Remove non-ascii characters
Change-Id: Iedb78e24a286a51830c85724af0179995ed553be
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/soc/rockchip/rk3399/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3399/clock.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 980adf5000..5422deb5cf 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -344,12 +344,12 @@ static void rkclk_set_pll(u32 *pll_con, const struct pll_div *div) /* * Configure the DPLL spread spectrum feature on memory clock. * Configure sequence: - * 1. PLL been configured as frac mode, and DACPD should be set to 1’b0. + * 1. PLL been configured as frac mode, and DACPD should be set to 1'b0. * 2. Configure DOWNSPERAD, SPREAD, DIVVAL(option: configure xPLL_CON5 with * extern wave table). - * 3. set ssmod_disable_sscg = 1’b0, and set ssmod_bp = 1’b0. - * 4. Assert RESET = 1’b1 to SSMOD. - * 5. RESET = 1’b0 on SSMOD. + * 3. set ssmod_disable_sscg = 1'b0, and set ssmod_bp = 1'b0. + * 4. Assert RESET = 1'b1 to SSMOD. + * 5. RESET = 1'b0 on SSMOD. * 6. Adjust SPREAD/DIVVAL/DOWNSPREAD. */ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) @@ -385,13 +385,13 @@ static void rkclk_set_dpllssc(struct pll_div *dpll_cfg) * value of SPREAD. * SPREAD[4:0] Center Spread Down Spread * 0 0 0 - * 1 ±0.1% -0.10% - * 2 ±0.2% -0.20% - * 3 ±0.3% -0.30% - * 4 ±0.4% -0.40% - * 5 ±0.5% -0.50% + * 1 +/-0.1% -0.10% + * 2 +/-0.2% -0.20% + * 3 +/-0.3% -0.30% + * 4 +/-0.4% -0.40% + * 5 +/-0.5% -0.50% * ... - * 31 ±3.1% -3.10% + * 31 +/-3.1% -3.10% */ write32(&cru_ptr->dpll_con[4], RK_CLRSETBITS(PLL_SSMOD_DIVVAL_MASK << PLL_SSMOD_DIVVAL_SHIFT, |