mb/google/volteer/variants: Set TCSS PCIe RP0 to hidden by default

Set the default state of the TCSS PCIe RP0 to hidden so that coreboot
does not allocate resources to this hotplug root port.  The default
behavior on the reference design is that there is only one USB4 port
attached to port C1 while port C0 is only a USB3 port.

Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and
C1 ports, so these boards change the default to 'on' so that coreboot
does allocate resources for the hotplug port.

BUG=b:159143739
BRANCH=volteer
TEST=build volteer and voxel and check the resulting static.c to
ensure the device is hidden or not.  Also boot with the two different
configurations and ensure resources are assigned or not.  Finally
check that S0ix still functions with the C0 port set to 'hidden'
after authorizing a PCIe tunnel on port C1.

Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

0 files changed, 0 insertions, 0 deletions