rockchip: rk3399: enable mmu

This patch initialize MMU and config mmu ranges for rk3399.

During the bootblock phase, mark the max dram size supported(4GiB)
as device memory because the mmio space start at 0xF8000000, and
_sram as secure memory.
After ddr setup in romstage, remark whole dram as cached memory
except the _dma_coherent range.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot

Change-Id: I0cd4abb8c30b73d87d8ba6f964edd42bdf4813fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc22ab0c16d8107c217db1629286d5ff1c4bc5b3
Original-Change-Id: I66bfde396036d7a66b29517937a28f0767635066
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/332387
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14708
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 718426b137..40c652fcf2 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -23,6 +23,7 @@ bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 endif
 bootblock-y += bootblock.c
 bootblock-y += clock.c
+bootblock-y += mmu_operations.c
 bootblock-y += timer.c
 
 verstage-y += ../common/cbmem.c
@@ -39,6 +40,7 @@ romstage-y += sdram.c
 romstage-y += ../common/spi.c
 romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
 romstage-y += clock.c
+romstage-y += mmu_operations.c
 romstage-y += timer.c
 romstage-y += romstage.c