rk3288: add gpio

BUG=chrome-os-partner:29778
TEST=Build coreboot

Change-Id: I63b4a62f624d34f7028321cb4576cbdb9cd10817
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3606d7eb06d66e23f4ee7ecb6862d23bde3acfd2
Original-Change-Id: I3e0cff1c6de464a8a79e30e239cfb0960cbae253
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209460
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/8864
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

3 files changed, 162 insertions, 0 deletions

diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc
index e6f6336c39..4818cafb11 100644
--- a/src/soc/rockchip/rk3288/Makefile.inc
+++ b/src/soc/rockchip/rk3288/Makefile.inc
@@ -36,15 +36,18 @@ romstage-y += monotonic_timer.c
 romstage-$(CONFIG_DRIVERS_UART) += uart.c
 romstage-y += i2c.c
 romstage-y += clock.c
+romstage-y += gpio.c
 romstage-y += spi.c
 romstage-y += media.c
 
+
 ramstage-y += cbmem.c
 ramstage-y += timer.c
 ramstage-y += monotonic_timer.c
 ramstage-y += i2c.c
 ramstage-y += clock.c
 ramstage-y += spi.c
+ramstage-y += gpio.c
 ramstage-y += media.c
 ramstage-$(CONFIG_DRIVERS_UART) += uart.c
 
diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c
new file mode 100755
index 0000000000..46ef2eb114
--- /dev/null
+++ b/src/soc/rockchip/rk3288/gpio.c
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include "cpu.h"
+#include "gpio.h"
+#include "pmu.h"
+
+struct rk3288_gpio_regs *gpio_port[] = {
+	(struct rk3288_gpio_regs *)0xff750000,
+	(struct rk3288_gpio_regs *)0xff780000,
+	(struct rk3288_gpio_regs *)0xff790000,
+	(struct rk3288_gpio_regs *)0xff7a0000,
+	(struct rk3288_gpio_regs *)0xff7b0000,
+	(struct rk3288_gpio_regs *)0xff7c0000,
+	(struct rk3288_gpio_regs *)0xff7d0000,
+	(struct rk3288_gpio_regs *)0xff7e0000,
+	(struct rk3288_gpio_regs *)0xff7f0000
+};
+
+enum {
+	PULLNONE = 0,
+	PULLUP,
+	PULLDOWN
+};
+
+#define PMU_GPIO_PORT 0
+
+static void __gpio_input(gpio_t gpio, u32 pull)
+{
+	clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
+	if (gpio.port == PMU_GPIO_PORT)
+		clrsetbits_le32(&rk3288_pmu->gpio0pull[gpio.bank],
+				3 << (gpio.idx * 2),  pull << (gpio.idx * 2));
+	else
+		writel(RK_CLRSETBITS(3 << (gpio.idx * 2),
+			pull << (gpio.idx * 2)),
+			&rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank]);
+}
+
+void gpio_input(gpio_t gpio)
+{
+	__gpio_input(gpio, PULLNONE);
+}
+
+void gpio_input_pulldown(gpio_t gpio)
+{
+	__gpio_input(gpio, PULLDOWN);
+}
+
+void gpio_input_pullup(gpio_t gpio)
+{
+	__gpio_input(gpio, PULLUP);
+}
+
+int gpio_get_in_value(gpio_t gpio)
+{
+	return (readl(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1;
+}
+
+void gpio_output(gpio_t gpio, int value)
+{
+	setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num);
+	clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num,
+							   !!value << gpio.num);
+}
diff --git a/src/soc/rockchip/rk3288/gpio.h b/src/soc/rockchip/rk3288/gpio.h
new file mode 100755
index 0000000000..6cac6cbdec
--- /dev/null
+++ b/src/soc/rockchip/rk3288/gpio.h
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3288_GPIO_H__
+#define __SOC_ROCKCHIP_RK3288_GPIO_H__
+
+#include "addressmap.h"
+#include "grf.h"
+
+struct rk3288_gpio_regs {
+	u32 swporta_dr;
+	u32 swporta_ddr;
+	u32 reserved0[(0x30 - 0x08) / 4];
+	u32 inten;
+	u32 intmask;
+	u32 inttype_level;
+	u32 int_polarity;
+	u32 int_status;
+	u32 int_rawstatus;
+	u32 debounce;
+	u32 porta_eoi;
+	u32 ext_porta;
+	u32 reserved1[(0x60 - 0x54) / 4];
+	u32 ls_sync;
+};
+check_member(rk3288_gpio_regs, ls_sync, 0x60);
+
+typedef union {
+	u32 raw;
+	struct {
+		u16 port;
+		union {
+			struct {
+				u16 num:5;
+				u16 :11;
+			};
+			struct {
+				u16 idx:3;
+				u16 bank:2;
+				u16 :11;
+			};
+		};
+	};
+} gpio_t;
+
+enum {
+	GPIO_A = 0,
+	GPIO_B,
+	GPIO_C,
+	GPIO_D,
+};
+
+void gpio_input(gpio_t gpio);
+void gpio_input_pulldown(gpio_t gpio);
+void gpio_input_pullup(gpio_t gpio);
+void gpio_output(gpio_t gpio, int value);
+int gpio_get_in_value(gpio_t gpio);
+
+#endif	/* _ASM_ROCKCHIP_GPIO_H_ */