coreboot: rk3288: Add a stub implementation of the rk3288 SOC

Most things still needs to be filled in, but this will allow us to build boards which use this SOC.

BUG=chrome-os-partner:29778
TEST=emerge-veyron coreboot

Original-Change-Id: If643d620c5fb8951faaf1ccde400a8e9ed7db3bc
Original-Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205069
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2f72473a8c2b3fe21d77b351338e6209035878fb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I53fd0ced42f6ef191d7bf80d8b823bb880344239
Reviewed-on: http://review.coreboot.org/8653
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 167 insertions, 0 deletions

diff --git a/src/soc/rockchip/rk3288/uart.c b/src/soc/rockchip/rk3288/uart.c
new file mode 100644
index 0000000000..60b14a3209
--- /dev/null
+++ b/src/soc/rockchip/rk3288/uart.c
@@ -0,0 +1,167 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Rockchip Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/uart.h>
+#include <arch/io.h>
+#include <boot/coreboot_tables.h>
+#include <console/console.h>	/* for __console definition */
+#include <stdint.h>
+#include <drivers/uart/uart8250reg.h>
+
+/*
+ * TODO: Use DRIVERS_UART_8250MEM driver instead.
+ * There is an issue in the IO call functions where x86 and ARM
+ * ordering is reversed. This 8250MEM driver uses the x86 convention.
+ * This driver can be replaced once the IO calls are sorted.
+ */
+
+struct rk3288_uart {
+	union {
+		uint32_t thr; /* Transmit holding register. */
+		uint32_t rbr; /* Receive buffer register. */
+		uint32_t dll; /* Divisor latch lsb. */
+	};
+	union {
+		uint32_t ier; /* Interrupt enable register. */
+		uint32_t dlm; /* Divisor latch msb. */
+	};
+	union {
+		uint32_t iir; /* Interrupt identification register. */
+		uint32_t fcr; /* FIFO control register. */
+	};
+	uint32_t lcr; /* Line control register. */
+	uint32_t mcr; /* Modem control register. */
+	uint32_t lsr; /* Line status register. */
+	uint32_t msr; /* Modem status register. */
+	uint32_t scr;
+	uint32_t reserved1[(0x30 - 0x20) / 4];
+	uint32_t srbr[(0x70 - 0x30) / 4];
+	uint32_t far;
+	uint32_t tfr;
+	uint32_t rfw;
+	uint32_t usr;
+	uint32_t tfl;
+	uint32_t rfl;
+	uint32_t srr;
+	uint32_t srts;
+	uint32_t sbcr;
+	uint32_t sdmam;
+	uint32_t sfe;
+	uint32_t srt;
+	uint32_t stet;
+	uint32_t htx;
+	uint32_t dmasa;
+	uint32_t reserver2[(0xf4 - 0xac) / 4];
+	uint32_t cpr;
+	uint32_t ucv;
+	uint32_t ctr;
+} __attribute__ ((packed));
+
+
+static struct rk3288_uart * const uart_ptr =
+	(void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+
+static void rk3288_uart_tx_flush(void);
+static int rk3288_uart_tst_byte(void);
+
+static void rk3288_uart_init(void)
+{
+	/* FIXME: Use a hardcoded divisor for now.
+	 * uint16_t divisor = (u16) uart_baudrate_divisor(default_baudrate(),
+	 *	uart_platform_refclk(), 16)
+	 */
+	const unsigned divisor = 13;
+	const uint8_t line_config = UART8250_LCR_WLS_8; // 8n1
+
+	rk3288_uart_tx_flush();
+
+	// Disable interrupts.
+	writel(0, &uart_ptr->ier);
+	// Force DTR and RTS to high.
+	writel(UART8250_MCR_DTR | UART8250_MCR_RTS, &uart_ptr->mcr);
+	// Set line configuration, access divisor latches.
+	writel(UART8250_LCR_DLAB | line_config, &uart_ptr->lcr);
+	// Set the divisor.
+	writel(divisor & 0xff, &uart_ptr->dll);
+	writel((divisor >> 8) & 0xff, &uart_ptr->dlm);
+	// Hide the divisor latches.
+	writel(line_config, &uart_ptr->lcr);
+	// Enable FIFOs, and clear receive and transmit.
+	writel(UART8250_FCR_FIFO_EN |
+		UART8250_FCR_CLEAR_RCVR |
+		UART8250_FCR_CLEAR_XMIT, &uart_ptr->fcr);
+}
+
+static void rk3288_uart_tx_byte(unsigned char data)
+{
+	while (!(readl(&uart_ptr->lsr) & UART8250_LSR_THRE));
+	writel(data, &uart_ptr->thr);
+}
+
+static void rk3288_uart_tx_flush(void)
+{
+	while (!(readl(&uart_ptr->lsr) & UART8250_LSR_TEMT));
+}
+
+static unsigned char rk3288_uart_rx_byte(void)
+{
+	if (!rk3288_uart_tst_byte())
+		return 0;
+	return readl(&uart_ptr->rbr);
+}
+
+static int rk3288_uart_tst_byte(void)
+{
+	return (readl(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
+}
+
+
+
+void uart_init(int idx)
+{
+	rk3288_uart_init();
+}
+
+unsigned char uart_rx_byte(int idx)
+{
+	return rk3288_uart_rx_byte();
+}
+
+void uart_tx_byte(int idx, unsigned char data)
+{
+	rk3288_uart_tx_byte(data);
+}
+
+void uart_tx_flush(int idx)
+{
+	rk3288_uart_tx_flush();
+}
+
+#ifndef __PRE_RAM__
+void uart_fill_lb(void *data)
+{
+	struct lb_serial serial;
+	serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+	serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+	serial.baud = default_baudrate();
+	lb_add_serial(&serial, data);
+
+	lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
+}
+#endif