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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2020-10-28 22:28:07 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-01 07:49:47 +0000 |
| commit | ae81d59ecaf050f7e14adb136560e993a98164cf (patch) | |
| tree | 7d81c6e58c85605d91520fa15d12fff8a9ba94e0 /src/soc/rockchip/rk3288/timer.c | |
| parent | 4cb8776c31ceb4a5b9e353b2e9b2a4f751e1dc54 (diff) | |
mb/intel/adlrvp: Add support for LPDDR5
This patch adds LPDDR5 memory configuration parameters to FSP.
TEST=Able to pass FSP-M MRC training on LPDDR5 RVP.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Diffstat (limited to 'src/soc/rockchip/rk3288/timer.c')
0 files changed, 0 insertions, 0 deletions