aboutsummaryrefslogtreecommitdiff
path: root/src/soc/rockchip/rk3288/hdmi.c
diff options
context:
space:
mode:
authorDavid Hendricks <dhendrix@chromium.org>2015-07-30 18:49:48 -0700
committerPatrick Georgi <pgeorgi@google.com>2015-08-28 06:42:03 +0000
commit7dbf9c6747ccdfa8b993d3843a22722742957611 (patch)
treea069e96ccfc13888c6df8a3d91a5864fc8acbc8e /src/soc/rockchip/rk3288/hdmi.c
parenta3b898aaf0ddf48fc3a577f4c39dd1d8acf31b6f (diff)
edid: Use edid_mode struct to reduce redundancy
This replaces various timing mode parameters parameters with an edid_mode struct within the edid struct. BUG=none BRANCH=firmware-veyron TEST=built and booted on Mickey, saw display come up, also compiled for link,falco,peppy,rambi,nyan_big,rush,smaug [pg: extended to also cover peach_pit, daisy and lenovo/t530] Change-Id: Icd0d67bfd3c422be087976261806b9525b2b9c7e Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Original-Commit-Id: abcbf25c81b25fadf71cae106e01b3e36391f5e9 Original-Change-Id: I1bfba5b06a708d042286db56b37f67302f61fff6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289964 Original-Reviewed-by: Yakir Yang <ykk@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11388 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/hdmi.c')
-rw-r--r--src/soc/rockchip/rk3288/hdmi.c36
1 files changed, 18 insertions, 18 deletions
diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c
index 582c834c5c..a7a9c400d3 100644
--- a/src/soc/rockchip/rk3288/hdmi.c
+++ b/src/soc/rockchip/rk3288/hdmi.c
@@ -494,11 +494,11 @@ static void hdmi_av_composer(const struct edid *edid)
/* set up hdmi_fc_invidconf */
inv_val = HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE;
- inv_val |= ((edid->pvsync == '+') ?
+ inv_val |= ((edid->mode.pvsync == '+') ?
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH :
HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW);
- inv_val |= ((edid->phsync == '+') ?
+ inv_val |= ((edid->mode.phsync == '+') ?
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH :
HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW);
@@ -517,33 +517,33 @@ static void hdmi_av_composer(const struct edid *edid)
write32(&hdmi_regs->fc_invidconf, inv_val);
/* set up horizontal active pixel width */
- write32(&hdmi_regs->fc_inhactv1, edid->ha >> 8);
- write32(&hdmi_regs->fc_inhactv0, edid->ha);
+ write32(&hdmi_regs->fc_inhactv1, edid->mode.ha >> 8);
+ write32(&hdmi_regs->fc_inhactv0, edid->mode.ha);
/* set up vertical active lines */
- write32(&hdmi_regs->fc_invactv1, edid->va >> 8);
- write32(&hdmi_regs->fc_invactv0, edid->va);
+ write32(&hdmi_regs->fc_invactv1, edid->mode.va >> 8);
+ write32(&hdmi_regs->fc_invactv0, edid->mode.va);
/* set up horizontal blanking pixel region width */
- write32(&hdmi_regs->fc_inhblank1, edid->hbl >> 8);
- write32(&hdmi_regs->fc_inhblank0, edid->hbl);
+ write32(&hdmi_regs->fc_inhblank1, edid->mode.hbl >> 8);
+ write32(&hdmi_regs->fc_inhblank0, edid->mode.hbl);
/* set up vertical blanking pixel region width */
- write32(&hdmi_regs->fc_invblank, edid->vbl);
+ write32(&hdmi_regs->fc_invblank, edid->mode.vbl);
/* set up hsync active edge delay width (in pixel clks) */
- write32(&hdmi_regs->fc_hsyncindelay1, edid->hso >> 8);
- write32(&hdmi_regs->fc_hsyncindelay0, edid->hso);
+ write32(&hdmi_regs->fc_hsyncindelay1, edid->mode.hso >> 8);
+ write32(&hdmi_regs->fc_hsyncindelay0, edid->mode.hso);
/* set up vsync active edge delay (in lines) */
- write32(&hdmi_regs->fc_vsyncindelay, edid->vso);
+ write32(&hdmi_regs->fc_vsyncindelay, edid->mode.vso);
/* set up hsync active pulse width (in pixel clks) */
- write32(&hdmi_regs->fc_hsyncinwidth1, edid->hspw >> 8);
- write32(&hdmi_regs->fc_hsyncinwidth0, edid->hspw);
+ write32(&hdmi_regs->fc_hsyncinwidth1, edid->mode.hspw >> 8);
+ write32(&hdmi_regs->fc_hsyncinwidth0, edid->mode.hspw);
/* set up vsync active edge delay (in lines) */
- write32(&hdmi_regs->fc_vsyncinwidth, edid->vspw);
+ write32(&hdmi_regs->fc_vsyncinwidth, edid->mode.vspw);
}
/* hdmi initialization step b.4 */
@@ -613,11 +613,11 @@ static int hdmi_setup(const struct edid *edid)
int ret;
hdmi_debug("hdmi, mode info : clock %d hdis %d vdis %d\n",
- edid->pixel_clock, edid->ha, edid->va);
+ edid->mode.pixel_clock, edid->mode.ha, edid->mode.va);
hdmi_av_composer(edid);
- ret = hdmi_phy_init(edid->pixel_clock);
+ ret = hdmi_phy_init(edid->mode.pixel_clock);
if (ret)
return ret;
@@ -625,7 +625,7 @@ static int hdmi_setup(const struct edid *edid)
hdmi_audio_fifo_reset();
hdmi_audio_set_format();
- hdmi_audio_set_samplerate(edid->pixel_clock);
+ hdmi_audio_set_samplerate(edid->mode.pixel_clock);
hdmi_video_packetize();
hdmi_video_csc();