diff options
| author | Julius Werner <jwerner@chromium.org> | 2014-12-16 22:48:26 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-04-15 16:45:04 +0200 |
| commit | 33df49519eb19556497bb3fdf442b058be324895 (patch) | |
| tree | 050eb22ffbef21c9dc85d5fbbe2eadcd2c715f88 /src/soc/rockchip/rk3288/clock.c | |
| parent | 64c775624c8d717757f0cac430f915c7496cf17a (diff) | |
rk3288: Implement support for CRYPTO module and use it in vboot hashing
This patch implements support for the CRYPTO module in RK3288 and ties
it into the new vboot vb2ex_hwcrypto API. We only implement SHA256 for
now, since the engine doesn't support SHA512 and it's very unlikely that
we'll ever use SHA1 for anything again.
BRANCH=None
BUG=chrome-os-partner:32987
TEST=Booted Pinky, confirmed that it uses the hardware crypto engine and
that firmware body hashing time dropped to about 1.5ms (from over 70ms).
Change-Id: I91d0860b42b93d690d2fa083324d343efe7da5f1
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: e60d42cbffd0748e13bfe1a281877460ecde936b
Original-Change-Id: I92510082b311a48a56224a4fc44b1bbce39b17ac
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/236436
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: http://review.coreboot.org/9641
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index ab12e8c896..d7420ea8d6 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -493,6 +493,16 @@ void rkclk_configure_i2s(unsigned int hz) writel(d << 16 | n, &cru_ptr->cru_clksel_con[8]); } +void rkclk_configure_crypto(unsigned int hz) +{ + u32 div = PD_BUS_ACLK_HZ / hz; + + assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ)); + assert(hz <= 150*MHz); /* Suggested max in TRM. */ + writel(RK_CLRSETBITS(0x3 << 6, (div - 1) << 6), + &cru_ptr->cru_clksel_con[26]); +} + void rkclk_configure_tsadc(unsigned int hz) { u32 div; |