diff options
| author | David Hendricks <dhendrix@chromium.org> | 2015-09-02 18:10:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-09-08 11:50:50 +0000 |
| commit | 4bd65e1c0cd53802abd3598c03d28b82a11be46d (patch) | |
| tree | 888ea67501c02c7b34972e9f208815c04f45c1aa /src/soc/rockchip/rk3288/clock.c | |
| parent | 68957b33ed4f9261bd74217aa58e9e1e08ac2aea (diff) | |
rk3288: Allow board-specific APLL (CPU clock) settings
This changes the API to rkclk_configure_cpu() such that we can pass
in the desired APLL frequency in each veyron board's bootblock.c.
Devices with a constrainted form facter (rialto and possibly mickey)
will use this to run firmware at a slower speed to mitigate risk
of thermal issues (due to the RK808, not the RK3288).
BUG=chrome-os-partner:42054
BRANCH=none
TEST=amstan says rialto is noticably cooler (and slower)
Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb
Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297190
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
| -rw-r--r-- | src/soc/rockchip/rk3288/clock.c | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index e4d2e3eb98..31901e7ec6 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -73,10 +73,17 @@ static struct rk3288_cru_reg * const cru_ptr = (void *)CRU_BASE; "divisors on line " STRINGIFY(__LINE__)); /* Keep divisors as low as possible to reduce jitter and power usage. */ -static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 1); static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); +/* See linux/drivers/clk/rockchip/clk-rk3288.c for more APLL combinations */ +static const struct pll_div apll_1800_cfg = PLL_DIVISORS(1800*MHz, 1, 1); +static const struct pll_div apll_1392_cfg = PLL_DIVISORS(1392*MHz, 1, 1); +static const struct pll_div *apll_cfgs[] = { + [APLL_1800_MHZ] = &apll_1800_cfg, + [APLL_1392_MHZ] = &apll_1392_cfg, +}; + /*******************PLL CON0 BITS***************************/ #define PLL_OD_MSK (0x0F) @@ -314,13 +321,13 @@ void rkclk_init(void) } -void rkclk_configure_cpu(void) +void rkclk_configure_cpu(enum apll_frequencies apll_freq) { /* pll enter slow-mode */ write32(&cru_ptr->cru_mode_con, RK_CLRSETBITS(APLL_MODE_MSK, APLL_MODE_SLOW)); - rkclk_set_pll(&cru_ptr->cru_apll_con[0], &apll_init_cfg); + rkclk_set_pll(&cru_ptr->cru_apll_con[0], apll_cfgs[apll_freq]); /* waiting for pll lock */ while (1) { |