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authorhuang lin <hl@rock-chips.com>2016-03-02 18:46:24 +0800
committerPatrick Georgi <pgeorgi@google.com>2016-04-13 23:38:31 +0200
commitd4c175b97b7c3503e1debdf45e20882cd12bec3a (patch)
treeb611b1b8688fa30e23f4a768a003607ab147c944 /src/soc/rockchip/rk3288/clock.c
parentc14b54dd170cb2fae16a5086134208caba0593f8 (diff)
rockchip/rk3288: refactor i2c interface to allow support of rk3399
Both SOCs use the same base i2c controller, the difference mostly being the number of interfaces and distribution of the interfaces' registers between register files. Upload check was complaining about misspelled labels, fixed them to pacify the check. With this patch in place it is easy to add support for 3399. BUG=none BRANCH=none TEST=brought up veyron_mickey all the way to booting the kernel. It properly recognized the TPM and the edid of the panel, proving that i2c interface is operational. Change-Id: I656640feabd0fc01d2c3b98bc5bd1e5f76f063f6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 82832dfd4948ce9a5034ea8ec0463ab82f0f5754 Original-Change-Id: I4829ea53e5f4cb055793d9a7c9957d6438138956 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/337971 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/14335 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/rk3288/clock.c')
-rw-r--r--src/soc/rockchip/rk3288/clock.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c
index 01f1e9ff23..bb5b846c04 100644
--- a/src/soc/rockchip/rk3288/clock.c
+++ b/src/soc/rockchip/rk3288/clock.c
@@ -21,6 +21,7 @@
#include <soc/addressmap.h>
#include <soc/clock.h>
#include <soc/grf.h>
+#include <soc/i2c.h>
#include <soc/soc.h>
#include <stdint.h>
#include <stdlib.h>
@@ -667,3 +668,25 @@ int rkclk_was_watchdog_reset(void)
/* Bits 5 and 4 are "second" and "first" global watchdog reset. */
return read32(&cru_ptr->cru_glb_rst_st) & 0x30;
}
+
+unsigned rkclk_i2c_clock_for_bus(unsigned bus)
+{
+ /*i2c0,i2c2 src clk from pd_bus_pclk
+ other i2c src clk from peri_pclk
+ */
+ switch (bus) {
+ case 0:
+ case 2:
+ return PD_BUS_PCLK_HZ;
+
+ case 1:
+ case 3:
+ case 4:
+ case 5:
+ return PERI_PCLK_HZ;
+
+ default:
+ return -1; /* Should never happen. */
+ }
+
+}