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authorLee Leahy <leroy.p.leahy@intel.com>2016-05-07 09:04:46 -0700
committerLeroy P Leahy <leroy.p.leahy@intel.com>2016-05-09 18:45:44 +0200
commit6ec72c9b4f4a903d9a451bc17629e679399aa9ee (patch)
tree815f70ba90e3646911d8380d803c823f1fefb507 /src/soc/rockchip/rk3288/Kconfig
parent148762110c8a00c88b8e0326ec69dc7392bf3739 (diff)
drivers/uart: Use uart_platform_refclk for all UART models
Allow the platform to override the input clock for the UART by implementing the routine uart_platform_refclk and setting the Kconfig value UART_OVERRIDE_REFCLK. Provide a default uart_platform_refclk routine which is disabled when UART_OVERRIDE_REFCLK is selected. This works around ROMCC not supporting weak routines. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: If4afc45a828e5ba935fecb6d95b239625e912d14 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/14612 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3288/Kconfig')
-rw-r--r--src/soc/rockchip/rk3288/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 8b15d3dc45..0f394b18b4 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -27,6 +27,7 @@ config SOC_ROCKCHIP_RK3288
select UNCOMPRESSED_RAMSTAGE
select GENERIC_GPIO_LIB
select RTC
+ select UART_OVERRIDE_REFCLK
if SOC_ROCKCHIP_RK3288