diff options
| author | Daisuke Nojiri <dnojiri@chromium.org> | 2014-09-24 09:39:16 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@google.com> | 2015-04-02 20:46:17 +0200 |
| commit | 5c2988c4616d8326f56037e7ef5e8280c134ef7d (patch) | |
| tree | 4b9d802bdb193e4ea12399ddec69e1b3965cbba5 /src/soc/rockchip/rk3288/Kconfig | |
| parent | 8d9a1bd5a84df71965488bfc49f07bdc1dcc1f9a (diff) | |
veyron: select rw romstage using vboot2
this change makes veyron pinky to select a rw romstage using vboot2.
BUG=None
TEST=Booted Veyron Pinky. Verified firmware selection in the log.
BRANCH=None
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
CQ-DEPEND=CL:219100
Original-Change-Id: Ia1cfdacde9f8b17b00e7772a02e0d266afedb82f
Original-Reviewed-on: https://chromium-review.googlesource.com/219103
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 69c1e4b9ee200645d38d28165389aa85ef9b36cd)
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7b4a2db8bcb95038dfb55bb7ceee66ac4a6c9475
Reviewed-on: http://review.coreboot.org/9234
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/soc/rockchip/rk3288/Kconfig')
| -rw-r--r-- | src/soc/rockchip/rk3288/Kconfig | 21 |
1 files changed, 17 insertions, 4 deletions
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index 359ce2f57d..aa4ee34a07 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -29,7 +29,6 @@ config SOC_ROCKCHIP_RK3288 select HAVE_UART_MEMORY_MAPPED select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select DYNAMIC_CBMEM if SOC_ROCKCHIP_RK3288 @@ -49,9 +48,10 @@ config BOOTBLOCK_CPU_INIT # # 0xFF70_0000 TTB (16KB). # 0xFF70_4004 Bootblock (max 16KB-4B). -# 0xFF70_8000 ROM stage (max 40KB). +# 0xFF70_8000 verstage then romstage (max 40KB). # 0xFF71_2000 STACK (4KB). -# 0xFF71_3000 CBFS mapping cache (20K) +# 0xFF71_3000 CBFS mapping cache (4K) +# 0xFF71_4000 vboot work buffer (16K) # 0xFF71_7FFF End of iRAM. config SYS_SRAM_BASE @@ -74,6 +74,11 @@ config BOOTBLOCK_BASE hex default 0xff704004 +# with vboot2, romstage is loaded over the verstage space +config VERSTAGE_BASE + hex + default 0xff708000 + config ROMSTAGE_BASE hex "ROM STAGE BASE" default 0xff708000 @@ -100,7 +105,15 @@ config CBFS_SRAM_CACHE_ADDRESS config CBFS_SRAM_CACHE_SIZE hex "size of CBFS cache data" - default 0x00005000 + default 0x00001000 + +config VBOOT_WORK_BUFFER_ADDRESS + hex "memory address of vboot work buffer" + default 0xff714000 + +config VBOOT_WORK_BUFFER_SIZE + hex "size of vboot work buffer" + default 0x00004000 config CBFS_DRAM_CACHE_ADDRESS hex "dram memory address to put CBFS cache data" |