diff options
| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-05-04 15:54:37 +0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-05-18 20:14:21 +0200 |
| commit | c7f32a5bb444de3de22904cad1fac0f08b88ee8d (patch) | |
| tree | bbab73e5da11f40a31ebca915c7fd9d957bb6412 /src/soc/rockchip/common | |
| parent | 2d96be6484217bf070a1f0e8270661dc355033d6 (diff) | |
rockchip: rk3399: add routines to set vop clocks
Let vop aclk sources from CPLL, and vop dclk from NPLL.
The dclk freq is decided by the edid mode pixel_clock which
may require high accuracy like 252750KHz. The pll_para_config()
can calculate the dividers for PLL to output desired clock.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=check display with the other patches
Change-Id: I12cf27d3d1177a8b1c4cfbd7c0be10204e3d3142
Signed-off-by: Martin Roth <martinroth@google.com>
Original-Commit-Id: 0f019b055fffebe9ea3928aae1e25b0ad4feef81
Original-Change-Id: Icef58f87041905961772b69c6b8170d5a866a531
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/342335
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-on: https://review.coreboot.org/14846
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Diffstat (limited to 'src/soc/rockchip/common')
0 files changed, 0 insertions, 0 deletions