diff options
| author | Shelley Chen <shchen@chromium.org> | 2016-06-27 18:21:34 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-07-12 00:28:22 +0200 |
| commit | 5d49b4a4bcbc878256dac40ef834e07ea7101673 (patch) | |
| tree | 22c267fd8970de0bee61d007a8b07a45d3a4ea07 /src/soc/rockchip/common | |
| parent | 1592bfb77ee88bfaa6d64417aaf2e5f9b359e894 (diff) | |
google/gru: Read RAM & board ids from the ADC
- Update so that the RAM id is read from ADC instead of
hard-coded from the config array.
- Update the boardid readings so that they are bucketed instead
of within an error margin.
BRANCH=None
BUG=chrome-os-partner:54566,chrome-os-partner:53988
TEST=hexdump /proc/device-tree/firmware/coreboot/ram-code
and boardid when OS boots up. Also verified that
voltage read in debug output returns correct id.
Change-Id: I963406d8c440cd90c3024c814c0de61d35ebe2fd
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 068705a38734d2604f71c8a7b5bf2cc15b0f7045
Original-Change-Id: I1c847558d54a0f7f9427904eeda853074ebb0e2e
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/356584
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/15586
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/rockchip/common')
0 files changed, 0 insertions, 0 deletions