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authorDuncan Laurie <dlaurie@chromium.org>2018-03-26 02:25:07 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-03-28 06:44:02 +0000
commit2410cd937925df60934855c885a16c40d2d69739 (patch)
tree996e05982c0399a1f0e456f704bad1219be0a18b /src/soc/rockchip/common/spi.c
parent4c8fbc065874d352b2215739bae0e0ae8a04757e (diff)
soc/intel/cannonlake: Limit xDCI feature when VBOOT is enabled
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb. Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/rockchip/common/spi.c')
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