diff options
author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-04-20 20:35:09 +0800 |
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committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-09 08:43:28 +0200 |
commit | 015ae11bf6c68e2d693cd1cd258204de9de66516 (patch) | |
tree | 34248a987758a7d3e518df92c61a56aaab033a7a /src/soc/rockchip/common/gpio.c | |
parent | 4f17374dfd25db1bbb163c474de6dc6f8a7d9e84 (diff) |
rockchip: refactor gpio driver
The gpio of rockchip SoCs(rk3288 & rk3399) are the same IP,
moving the gpio code of rk3288 to common then can be reused on rk3399.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=build and boot into chromeos on veyron_jerry
Change-Id: I10a4b9d32afe60fd52512f2ad0007e9d2785033b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1c0c4b4b999790b0be7b0eeb70d2a7a86158f779
Original-Change-Id: If13b7760108831d81e8e8c950cdf61724d497b17
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/339846
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/rockchip/common/gpio.c')
-rw-r--r-- | src/soc/rockchip/common/gpio.c | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c new file mode 100644 index 0000000000..6f30229817 --- /dev/null +++ b/src/soc/rockchip/common/gpio.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <gpio.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/soc.h> +#include <stdlib.h> + +enum { + PULLNONE = 0, + PULLUP, + PULLDOWN +}; + +static void __gpio_input(gpio_t gpio, u32 pull) +{ + clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); + if (is_pmu_gpio(gpio)) + clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), + pull << (gpio.idx * 2)); + else + write32(gpio_grf_reg(gpio), RK_CLRSETBITS(3 << (gpio.idx * 2), + pull << (gpio.idx * 2))); +} + +void gpio_input(gpio_t gpio) +{ + __gpio_input(gpio, PULLNONE); +} + +void gpio_input_pulldown(gpio_t gpio) +{ + __gpio_input(gpio, PULLDOWN); +} + +void gpio_input_pullup(gpio_t gpio) +{ + __gpio_input(gpio, PULLUP); +} + +int gpio_get(gpio_t gpio) +{ + return (read32(&gpio_port[gpio.port]->ext_porta) >> gpio.num) & 0x1; +} + +void gpio_output(gpio_t gpio, int value) +{ + setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); + clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, + !!value << gpio.num); +} |