arm(64): Replace write32() and friends with writel()

This patch is a raw application of the following spatch to the
directories src/arch/arm(64)?, src/mainboard/<arm(64)-board>,
src/soc/<arm(64)-soc> and src/drivers/gic:

@@
expression A, V;
@@
- write32(V, A)
+ writel(V, A)
@@
expression A, V;
@@
- write16(V, A)
+ writew(V, A)
@@
expression A, V;
@@
- write8(V, A)
+ writeb(V, A)

This replaces all uses of write{32,16,8}() with write{l,w,b}()
which is currently equivalent and much more common. This is a
preparatory step that will allow us to easier flip them all at once to
the new write32(a,v) model.

BRANCH=none
BUG=chromium:451388
TEST=Compiled Cosmos, Daisy, Blaze, Pit, Ryu, Storm and Pinky.

Change-Id: I16016cd77780e7cadbabe7d8aa7ab465b95b8f09
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93f0ada19b429b4e30d67335b4e61d0f43597b24
Original-Change-Id: I1ac01c67efef4656607663253ed298ff4d0ef89d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254862
Reviewed-on: http://review.coreboot.org/9834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 34 insertions, 74 deletions

diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c
index fe7cfb83a8..0b770da94f 100644
--- a/src/soc/qualcomm/ipq806x/clock.c
+++ b/src/soc/qualcomm/ipq806x/clock.c
@@ -126,22 +126,17 @@ void nand_clock_config(void)
 void usb_clock_config(void)
 {
 	/* Magic clock initialization numbers, nobody knows how they work... */
-	write32(0x10, USB30_MASTER_CLK_CTL_REG);
-	write32(0x10, USB30_1_MASTER_CLK_CTL_REG);
-	write32(0x500DF, USB30_MASTER_CLK_MD);
-	write32(0xE40942, USB30_MASTER_CLK_NS);
-	write32(0x100D7, USB30_MOC_UTMI_CLK_MD);
-	write32(0xD80942, USB30_MOC_UTMI_CLK_NS);
-	write32(0x10, USB30_MOC_UTMI_CLK_CTL);
-	write32(0x10, USB30_1_MOC_UTMI_CLK_CTL);
-
-	write32(1 << 5 |		/* assert port2 HS PHY async reset */
-		1 << 4 |		/* assert master async reset */
-		1 << 3 |		/* assert sleep async reset */
-		1 << 2 |		/* assert MOC UTMI async reset */
-		1 << 1 |		/* assert power-on async reset */
-		1 << 0 |		/* assert PHY async reset */
-		0, USB30_RESET);
+	writel(0x10, USB30_MASTER_CLK_CTL_REG);
+	writel(0x10, USB30_1_MASTER_CLK_CTL_REG);
+	writel(0x500DF, USB30_MASTER_CLK_MD);
+	writel(0xE40942, USB30_MASTER_CLK_NS);
+	writel(0x100D7, USB30_MOC_UTMI_CLK_MD);
+	writel(0xD80942, USB30_MOC_UTMI_CLK_NS);
+	writel(0x10, USB30_MOC_UTMI_CLK_CTL);
+	writel(0x10, USB30_1_MOC_UTMI_CLK_CTL);
+
+	writel(1 << 5 | 1 << 4 | 1 << 3 | 1 << 2 | 1 << 1 | 1 << 0 | 0,
+	       USB30_RESET);
 	udelay(5);
-	write32(0, USB30_RESET);	/* deassert all USB resets again */
+	writel(0, USB30_RESET);	/* deassert all USB resets again */
 }
diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c
index fb89373953..69b3998624 100644
--- a/src/soc/qualcomm/ipq806x/usb.c
+++ b/src/soc/qualcomm/ipq806x/usb.c
@@ -101,33 +101,16 @@ static struct usb_dwc3 * const usb_host2_dwc3 = (void *)USB_HOST2_DWC3_BASE;
 
 static void setup_dwc3(struct usb_dwc3 *dwc3)
 {
-	write32(0x1 << 31 |	/* assert PHY soft reset */
-		0x1 << 25 |	/* (default) U1/U2 exit fail -> recovery? */
-		0x1 << 24 |	/* (default) activate PHY low power states */
-		0x1 << 19 |	/* (default) PHY low power delay value */
-		0x1 << 18 |	/* (default) activate PHY low power delay */
-		0x1 <<  1 |	/* (default) Tx deemphasis value */
-		0x1 <<  0 |	/* (default) elastic buffer mode */
-		0, &dwc3->usb3pipectl);
-
-	write32(0x1 << 31 |	/* assert PHY soft reset */
-		0x9 << 10 |	/* (default) PHY clock turnaround 8-bit UTMI+ */
-		0x1 <<  8 |	/* (default) enable PHY sleep in L1 */
-		0x1 <<  6 |	/* (default) enable PHY suspend */
-		0, &dwc3->usb2phycfg);
-
-	write32(0x2 << 19 |	/* (default) suspend clock scaling */
-		0x1 << 16 |	/* retry SS three times before HS downgrade */
-		0x1 << 12 |	/* port capability HOST */
-		0x1 << 11 |	/* assert core soft reset */
-		0x1 << 10 |	/* (default) sync ITP to refclk */
-		0x1 <<  2 |	/* U2 exit after 8us LFPS (instead of 248ns) */
-		0, &dwc3->ctl);
-
-	write32(0x32 << 22 |	/* (default) reference clock period in ns */
-		 0x1 << 15 |	/* (default) XHCI compliant device addressing */
-		0x10 <<  0 |	/* (default) devices time out after 32us */
-		0, &dwc3->uctl);
+	writel(0x1 << 31 | 0x1 << 25 | 0x1 << 24 | 0x1 << 19 | 0x1 << 18 | 0x1 << 1 | 0x1 << 0 | 0,
+	       &dwc3->usb3pipectl);
+
+	writel(0x1 << 31 | 0x9 << 10 | 0x1 << 8 | 0x1 << 6 | 0,
+	       &dwc3->usb2phycfg);
+
+	writel(0x2 << 19 | 0x1 << 16 | 0x1 << 12 | 0x1 << 11 | 0x1 << 10 | 0x1 << 2 | 0,
+	       &dwc3->ctl);
+
+	writel(0x32 << 22 | 0x1 << 15 | 0x10 << 0 | 0, &dwc3->uctl);
 
 	udelay(5);
 
@@ -138,34 +121,16 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
 
 static void setup_phy(struct usb_qc_phy *phy)
 {
-	write32(0x1  << 24 |	/* Indicate VBUS power present */
-		0x1  <<  8 |	/* Enable USB3 ref clock to prescaler */
-		0x1  <<  7 |	/* assert SS PHY reset */
-		0x19 <<  0 |	/* (default) reference clock multiplier */
-		0, &phy->ss_phy_ctrl);
-
-	write32(0x1 << 26 |	/* (default) unclamp DPSE/DMSE VLS */
-		0x1 << 25 |	/* (default) select freeclk for utmi_clk */
-		0x1 << 24 |	/* (default) unclamp DMSE VLS */
-		0x1 << 21 |	/* (default) enable UTMI clock */
-		0x1 << 20 |	/* set OTG VBUS as valid */
-		0x1 << 18 |	/* use ref clock from core */
-		0x1 << 17 |	/* (default) unclamp DPSE VLS */
-		0x1 << 11 |	/* force xo/bias/pll to stay on in suspend */
-		0x1 <<  9 | 	/* (default) unclamp IDHV */
-		0x1 <<  8 |	/* (default) unclamp VLS (again???) */
-		0x1 <<  7 |	/* (default) unclamp HV VLS */
-		0x7 <<  4 |	/* select frequency (no idea which one) */
-		0x1 <<  1 |	/* (default) "retention enable" */
-		0, &phy->hs_phy_ctrl);
-
-	write32(0x6e << 20 |	/* full TX swing amplitude */
-		0x20 << 14 |	/* (default) 6dB TX deemphasis */
-		0x17 <<  8 |	/* 3.5dB TX deemphasis */
-		0x9  <<  3 |	/* (default) LoS detector level */
-		0, &phy->ss_phy_param1);
-
-	write32(0x1 << 2, &phy->general_cfg);	/* set XHCI 1.00 compliance */
+	writel(0x1 << 24 | 0x1 << 8 | 0x1 << 7 | 0x19 << 0 | 0,
+	       &phy->ss_phy_ctrl);
+
+	writel(0x1 << 26 | 0x1 << 25 | 0x1 << 24 | 0x1 << 21 | 0x1 << 20 | 0x1 << 18 | 0x1 << 17 | 0x1 << 11 | 0x1 << 9 | 0x1 << 8 | 0x1 << 7 | 0x7 << 4 | 0x1 << 1 | 0,
+	       &phy->hs_phy_ctrl);
+
+	writel(0x6e << 20 | 0x20 << 14 | 0x17 << 8 | 0x9 << 3 | 0,
+	       &phy->ss_phy_param1);
+
+	writel(0x1 << 2, &phy->general_cfg);	/* set XHCI 1.00 compliance */
 
 	udelay(5);
 	clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */
@@ -176,9 +141,9 @@ static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data)
 	int usec = 100;
 
 	if (capture_reg)
-		write32(data, capture_reg);
+		writel(data, capture_reg);
 
-	write32(0x1 << 0, acknowledge_bit);
+	writel(0x1 << 0, acknowledge_bit);
 	while (read32(acknowledge_bit) && --usec)
 		udelay(1);