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authorJulius Werner <jwerner@chromium.org>2020-07-27 17:07:30 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-08-03 05:13:07 +0000
commitc435d3daa71005d190373ee00a6491520b542eaa (patch)
treebdd441caa441a62c857e8b60c0b1c5b927d7797a /src/soc/qualcomm
parent683ac6f204a8ae464a7f671b53084c99a0abce45 (diff)
qualcomm/sc7180: Fix TLMM assignments for GPIOs 29, 31 and 32
According to my SC7180 reference manual, these three GPIOs are in the NORTH TLMM, but our pin table lists them as SOUTH. That means all accesses our code has been doing to them have just been hitting empty address space. BUG=b:160115694 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: If9c03ac890a7975855394c2e08b8433472df204d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/soc/qualcomm')
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/gpio.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/soc/qualcomm/sc7180/include/soc/gpio.h b/src/soc/qualcomm/sc7180/include/soc/gpio.h
index e28d808893..8bfa36e9a0 100644
--- a/src/soc/qualcomm/sc7180/include/soc/gpio.h
+++ b/src/soc/qualcomm/sc7180/include/soc/gpio.h
@@ -159,10 +159,10 @@ enum {
RES_7),
PIN(28, SOUTH, CCI_I2C_SCL2, QUP0_L3, RES_3, RES_4, RES_5, RES_6,
RES_7),
- PIN(29, SOUTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(29, NORTH, GP_MN, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(30, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(31, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
- PIN(32, SOUTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(31, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
+ PIN(32, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(33, NORTH, RES_1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(34, SOUTH, QUP0_L0, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),
PIN(35, SOUTH, QUP0_L1, RES_2, RES_3, RES_4, RES_5, RES_6, RES_7),