Change all clrsetbits_leXX() to clrsetbitsXX()

This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.

This patch was created by running

 sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'

across the codebase and cleaning up formatting a bit.

Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

17 files changed, 100 insertions, 100 deletions

diff --git a/src/soc/qualcomm/ipq40xx/blsp.c b/src/soc/qualcomm/ipq40xx/blsp.c
index 75618c2461..099dc6e2c1 100644
--- a/src/soc/qualcomm/ipq40xx/blsp.c
+++ b/src/soc/qualcomm/ipq40xx/blsp.c
@@ -47,7 +47,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id)
 		return BLSP_UNSUPPORTED;
 
 	/* Configure Mini core to I2C core */
-	clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
+	clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
 
 	return BLSP_SUCCESS;
 }
diff --git a/src/soc/qualcomm/ipq40xx/clock.c b/src/soc/qualcomm/ipq40xx/clock.c
index e3d60e4749..bd1345e4ac 100644
--- a/src/soc/qualcomm/ipq40xx/clock.c
+++ b/src/soc/qualcomm/ipq40xx/clock.c
@@ -59,7 +59,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m,
 			2 << 12);	/* 13:12 Mode = Dual Edge */
 
 	/* Trigger update */
-	setbits_le32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1);
+	setbits32(GCC_BLSP1_UART_APPS_CMD_RCGR(blsp_uart), 1);
 
 	/* Wait for update */
 	for (i = 0; i < CLOCK_UPDATE_DELAY; i++) {
@@ -71,7 +71,7 @@ void uart_clock_config(unsigned int blsp_uart, unsigned int m,
 	}
 
 	/* Please refer to the comments in blsp_i2c_clock_config() */
-	setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
+	setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
 }
 
 /**
@@ -154,7 +154,7 @@ int blsp_i2c_clock_config(blsp_qup_id_t id)
 	 * the same bits is harmless. Hence repeating them here should be ok.
 	 * This will ensure root and branch clocks remain on.
 	 */
-	setbits_le32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
+	setbits32(GCC_CLK_BRANCH_ENA, BLSP1_AHB | BLSP1_SLEEP);
 
 	/* Src Sel 1 (fepll 200), Src Div 10.5 */
 	write32(clk[id].cfg, (1u << 8) | (20u << 0));
diff --git a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
index 930c912ee6..e4b613f7dc 100644
--- a/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq40xx/include/soc/iomap.h
@@ -47,8 +47,8 @@
  */
 #define readl_i(a)           read32((const void *)(a))
 #define writel_i(v,a)        write32((void *)a, v)
-#define clrsetbits_le32_i(addr, clear, set)  \
-	clrsetbits_le32(((void *)(addr)), (clear), (set))
+#define clrsetbits32_i(addr, clear, set)  \
+	clrsetbits32(((void *)(addr)), (clear), (set))
 
 #define GCC_CLK_CTL_REG			((void *)0x01800000u)
 #define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c
index b68e1cb864..3b0d63603d 100644
--- a/src/soc/qualcomm/ipq40xx/spi.c
+++ b/src/soc/qualcomm/ipq40xx/spi.c
@@ -240,7 +240,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * Configure Mini core to SPI core with Input Output enabled,
 	 * SPI master, N = 8 bits
 	 */
-	clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
+	clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
 						QUP_CONF_INPUT_MSK |
 						QUP_CONF_OUTPUT_MSK |
 						QUP_CONF_N_MASK,
@@ -253,7 +253,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * Configure Input first SPI protocol,
 	 * SPI master mode and no loopback
 	 */
-	clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
+	clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
 						SPI_CONFIG_NO_SLAVE_OPER_MSK,
 						SPI_CONFIG_NO_LOOP_BACK |
 						SPI_CONFIG_NO_SLAVE_OPER);
@@ -273,7 +273,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * INPUT_MODE = Block Mode
 	 * OUTPUT MODE = Block Mode
 	 */
-	clrsetbits_le32(ds->regs->qup_io_modes,
+	clrsetbits32(ds->regs->qup_io_modes,
 				QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
 				QUP_IO_MODES_INPUT_MODE_MSK |
 				QUP_IO_MODES_OUTPUT_MODE_MSK,
@@ -320,10 +320,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert)
 	struct ipq_spi_slave *ds = to_ipq_spi(slave);
 
 	if (assert)
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN);
 	else
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
 
 	return;
@@ -385,18 +385,18 @@ static void enable_io_config(struct ipq_spi_slave *ds,
 {
 
 	if (write_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
 	}
 
 	if (read_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 	}
 
diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c
index 15ea852ae8..5b7469c3fb 100644
--- a/src/soc/qualcomm/ipq806x/clock.c
+++ b/src/soc/qualcomm/ipq806x/clock.c
@@ -23,7 +23,7 @@
  */
 void uart_pll_vote_clk_enable(unsigned int clk_dummy)
 {
-	setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8));
+	setbits32(BB_PLL_ENA_SC0_REG, BIT(8));
 
 	if (!clk_dummy)
 		while ((read32(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0);
@@ -39,11 +39,11 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
 		unsigned int n)
 {
 	/* Assert MND reset. */
-	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
+	setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
 	/* Program M and D values. */
 	write32(GSBIn_UART_APPS_MD_REG(gsbi_port), MD16(m, n));
 	/* Deassert MND reset. */
-	clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
+	clrbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7));
 }
 
 /**
@@ -53,7 +53,7 @@ static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m,
  */
 static void uart_branch_clk_enable_reg(unsigned int gsbi_port)
 {
-	setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
+	setbits32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9));
 }
 
 /**
@@ -100,7 +100,7 @@ static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n,
  */
 static void uart_set_gsbi_clk(unsigned int gsbi_port)
 {
-	setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
+	setbits32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4));
 }
 
 /**
diff --git a/src/soc/qualcomm/ipq806x/include/soc/iomap.h b/src/soc/qualcomm/ipq806x/include/soc/iomap.h
index 76fd353bca..d501a81b39 100644
--- a/src/soc/qualcomm/ipq806x/include/soc/iomap.h
+++ b/src/soc/qualcomm/ipq806x/include/soc/iomap.h
@@ -46,8 +46,8 @@
  */
 #define readl_i(a)           read32((const void *)(a))
 #define writel_i(v,a)        write32((void *)a, v)
-#define clrsetbits_le32_i(addr, clear, set)  \
-	clrsetbits_le32(((void *)(addr)), (clear), (set))
+#define clrsetbits32_i(addr, clear, set)  \
+	clrsetbits32(((void *)(addr)), (clear), (set))
 
 #define MSM_CLK_CTL_BASE    ((void *)0x00900000)
 
diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c
index 183b33c20a..e2467b9ffd 100644
--- a/src/soc/qualcomm/ipq806x/spi.c
+++ b/src/soc/qualcomm/ipq806x/spi.c
@@ -307,7 +307,7 @@ static void gsbi_pin_config(unsigned int port_num, int cs_num)
 	unsigned int gpio;
 	unsigned int i;
 	/* Hold the GSBIn (core_num) core in reset */
-	clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)),
+	clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(port_num)),
 			GSBI1_RESET_MSK, GSBI1_RESET);
 
 	/*
@@ -348,11 +348,11 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds)
 	int ret;
 
 	/* Hold the GSBIn (core_num) core in reset */
-	clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)),
+	clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)),
 			GSBI1_RESET_MSK, GSBI1_RESET);
 
 	/* Disable GSBIn (core_num) QUP core clock branch */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK,
+	clrsetbits32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK,
 					QUP_CLK_BRANCH_DIS);
 
 	ret = check_qup_clk_state(ds->slave.bus, 1);
@@ -363,41 +363,41 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds)
 	}
 
 	/* Disable M/N:D counter and hold M/N:D counter in reset */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK),
+	clrsetbits32_i(ds->regs->qup_ns_reg, (MNCNTR_MSK | MNCNTR_RST_MSK),
 					(MNCNTR_RST_ENA | MNCNTR_DIS));
 
 	/* Disable GSBIn (core_num) QUP core clock root */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS);
+	clrsetbits32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_DIS);
 
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK,
+	clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_PLL_SRC_MSK,
 					GSBIn_PLL_SRC_PLL8);
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK,
+	clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_PRE_DIV_SEL_MSK,
 						(0 << GSBI_PRE_DIV_SEL_SHFT));
 
 	/* Program M/N:D values for GSBIn_QUP_APPS_CLK @50MHz */
-	clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK,
+	clrsetbits32_i(ds->regs->qup_md_reg, GSBIn_M_VAL_MSK,
 						(0x01 << GSBI_M_VAL_SHFT));
-	clrsetbits_le32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK,
+	clrsetbits32_i(ds->regs->qup_md_reg, GSBIn_D_VAL_MSK,
 						(0xF7 << GSBI_D_VAL_SHFT));
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK,
+	clrsetbits32_i(ds->regs->qup_ns_reg, GSBIn_N_VAL_MSK,
 						(0xF8 << GSBI_N_VAL_SHFT));
 
 	/* Set MNCNTR_MODE = 0: Bypass mode */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK,
+	clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_MODE_MSK,
 					MNCNTR_MODE_DUAL_EDGE);
 
 	/* De-assert the M/N:D counter reset */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS);
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN);
+	clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_RST_MSK, MNCNTR_RST_DIS);
+	clrsetbits32_i(ds->regs->qup_ns_reg, MNCNTR_MSK, MNCNTR_EN);
 
 	/*
 	 * Enable the GSBIn (core_num) QUP core clock root.
 	 * Keep MND counter disabled
 	 */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA);
+	clrsetbits32_i(ds->regs->qup_ns_reg, CLK_ROOT_ENA_MSK, CLK_ROOT_ENA);
 
 	/* Enable GSBIn (core_num) QUP core clock branch */
-	clrsetbits_le32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK,
+	clrsetbits32_i(ds->regs->qup_ns_reg, QUP_CLK_BRANCH_ENA_MSK,
 						QUP_CLK_BRANCH_ENA);
 
 	ret = check_qup_clk_state(ds->slave.bus, 0);
@@ -409,7 +409,7 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds)
 	}
 
 	/* Enable GSBIn (core_num) core clock branch */
-	clrsetbits_le32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)),
+	clrsetbits32_i(GSBIn_HCLK_CTL_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)),
 			GSBI_CLK_BRANCH_ENA_MSK, GSBI_CLK_BRANCH_ENA);
 
 	ret = check_hclk_state(ds->slave.bus, 0);
@@ -420,7 +420,7 @@ static int gsbi_clock_init(struct ipq_spi_slave *ds)
 	}
 
 	/* Release GSBIn (core_num) core from reset */
-	clrsetbits_le32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)),
+	clrsetbits32_i(GSBIn_RESET_REG(GSBI_IDX_TO_GSBI(ds->slave.bus)),
 						GSBI1_RESET_MSK, 0);
 	udelay(50);
 
@@ -541,14 +541,14 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 		return ret;
 
 	/* Configure GSBI_CTRL register to set protocol_mode to SPI:011 */
-	clrsetbits_le32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK,
+	clrsetbits32_i(ds->regs->gsbi_ctrl, PROTOCOL_CODE_MSK,
 					PROTOCOL_CODE_SPI);
 
 	/*
 	 * Configure Mini core to SPI core with Input Output enabled,
 	 * SPI master, N = 8 bits
 	 */
-	clrsetbits_le32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK |
+	clrsetbits32_i(ds->regs->qup_config, (QUP_CONFIG_MINI_CORE_MSK |
 					       SPI_QUP_CONF_INPUT_MSK |
 					       SPI_QUP_CONF_OUTPUT_MSK |
 					       SPI_BIT_WORD_MSK),
@@ -561,7 +561,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * Configure Input first SPI protocol,
 	 * SPI master mode and no loopback
 	 */
-	clrsetbits_le32_i(ds->regs->spi_config, (LOOP_BACK_MSK |
+	clrsetbits32_i(ds->regs->spi_config, (LOOP_BACK_MSK |
 					       SLAVE_OPERATION_MSK),
 					      (NO_LOOP_BACK |
 					       SLAVE_OPERATION));
@@ -581,7 +581,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds)
 	 * INPUT_MODE = Block Mode
 	 * OUTPUT MODE = Block Mode
 	 */
-	clrsetbits_le32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK |
+	clrsetbits32_i(ds->regs->qup_io_modes, (OUTPUT_BIT_SHIFT_MSK |
 						 INPUT_BLOCK_MODE_MSK |
 						 OUTPUT_BLOCK_MODE_MSK),
 						(OUTPUT_BIT_SHIFT_EN |
@@ -707,7 +707,7 @@ static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
 	 * Let's do the write side of the transaction first. Enable output
 	 * FIFO.
 	 */
-	clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK,
+	clrsetbits32_i(ds->regs->qup_config, SPI_QUP_CONF_OUTPUT_MSK,
 			  SPI_QUP_CONF_OUTPUT_ENA);
 
 	while (out_bytes) {
@@ -729,7 +729,7 @@ spi_receive:
 		goto out;
 
 	/* Enable input FIFO */
-	clrsetbits_le32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK,
+	clrsetbits32_i(ds->regs->qup_config, SPI_QUP_CONF_INPUT_MSK,
 			  SPI_QUP_CONF_INPUT_ENA);
 
 	while (in_bytes) {
diff --git a/src/soc/qualcomm/ipq806x/usb.c b/src/soc/qualcomm/ipq806x/usb.c
index 35285cd0d5..003bc7bf0b 100644
--- a/src/soc/qualcomm/ipq806x/usb.c
+++ b/src/soc/qualcomm/ipq806x/usb.c
@@ -127,9 +127,9 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
 
 	udelay(5);
 
-	clrbits_le32(&dwc3->ctl, 0x1 << 11);	/* deassert core soft reset */
-	clrbits_le32(&dwc3->usb2phycfg, 0x1 << 31);	/* PHY soft reset */
-	clrbits_le32(&dwc3->usb3pipectl, 0x1 << 31);	/* PHY soft reset */
+	clrbits32(&dwc3->ctl, 0x1 << 11);	/* deassert core soft reset */
+	clrbits32(&dwc3->usb2phycfg, 0x1 << 31);	/* PHY soft reset */
+	clrbits32(&dwc3->usb3pipectl, 0x1 << 31);	/* PHY soft reset */
 }
 
 static void setup_phy(struct usb_qc_phy *phy)
@@ -164,7 +164,7 @@ static void setup_phy(struct usb_qc_phy *phy)
 	write32(&phy->general_cfg, 0x1 << 2);	/* set XHCI 1.00 compliance */
 
 	udelay(5);
-	clrbits_le32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */
+	clrbits32(&phy->ss_phy_ctrl, 0x1 << 7); /* deassert SS PHY reset */
 }
 
 static void crport_handshake(void *capture_reg, void *acknowledge_bit, u32 data)
@@ -206,7 +206,7 @@ static void tune_phy(struct usb_qc_phy *phy)
 void setup_usb_host1(void)
 {
 	printk(BIOS_INFO, "Setting up USB HOST1 controller...\n");
-	setbits_le32(tcsr_usb_sel, 1 << 0);	/* Select DWC3 controller */
+	setbits32(tcsr_usb_sel, 1 << 0);	/* Select DWC3 controller */
 	setup_phy(usb_host1_phy);
 	setup_dwc3(usb_host1_dwc3);
 	tune_phy(usb_host1_phy);
@@ -215,7 +215,7 @@ void setup_usb_host1(void)
 void setup_usb_host2(void)
 {
 	printk(BIOS_INFO, "Setting up USB HOST2 controller...\n");
-	setbits_le32(tcsr_usb_sel, 1 << 1);	/* Select DWC3 controller */
+	setbits32(tcsr_usb_sel, 1 << 1);	/* Select DWC3 controller */
 	setup_phy(usb_host2_phy);
 	setup_dwc3(usb_host2_dwc3);
 	tune_phy(usb_host2_phy);
diff --git a/src/soc/qualcomm/qcs405/blsp.c b/src/soc/qualcomm/qcs405/blsp.c
index f185ea388a..42dc28d16c 100644
--- a/src/soc/qualcomm/qcs405/blsp.c
+++ b/src/soc/qualcomm/qcs405/blsp.c
@@ -59,7 +59,7 @@ blsp_return_t blsp_i2c_init(blsp_qup_id_t id)
 		return BLSP_ID_ERROR;
 
 	/* Configure Mini core to I2C core */
-	clrsetbits_le32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
+	clrsetbits32(base, BLSP_MINI_CORE_MASK, BLSP_MINI_CORE_I2C);
 
 	return BLSP_SUCCESS;
 }
diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c
index 37fd2c2098..da2e8a4603 100644
--- a/src/soc/qualcomm/qcs405/clock.c
+++ b/src/soc/qualcomm/qcs405/clock.c
@@ -96,7 +96,7 @@ struct clock_config spi_cfg[] = {
 static int clock_configure_gpll0(void)
 {
 	/* Keep existing GPLL0 configuration, in RUN mode @800Mhz. */
-	setbits_le32(&gcc->gpll0.user_ctl,
+	setbits32(&gcc->gpll0.user_ctl,
 			1 << CLK_CTL_GPLL_PLLOUT_LV_EARLY_SHFT |
 			1 << CLK_CTL_GPLL_PLLOUT_AUX2_SHFT |
 			1 << CLK_CTL_GPLL_PLLOUT_AUX_SHFT |
@@ -144,7 +144,7 @@ static int clock_configure(struct qcs405_clock *clk,
 				clk_cfg[idx].d_2);
 
 	/* Commit config to RCG*/
-	setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
+	setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
 
 	return 0;
 }
@@ -159,7 +159,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
 {
 
 	/* Set clock vote bit */
-	setbits_le32(vote_addr, BIT(vote_bit));
+	setbits32(vote_addr, BIT(vote_bit));
 
 	/* Ensure clock is enabled */
 	while (clock_is_off(cbcr_addr));
@@ -171,7 +171,7 @@ static int clock_enable(void *cbcr_addr)
 {
 
 	/* Set clock enable bit */
-	setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+	setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 
 	/* Ensure clock is enabled */
 	while (clock_is_off(cbcr_addr))
@@ -184,7 +184,7 @@ static int clock_disable(void *cbcr_addr)
 {
 
 	/* Set clock enable bit */
-	clrbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+	clrbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 	return 0;
 }
 
@@ -193,9 +193,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset)
 	struct qcs405_bcr *bcr = bcr_addr;
 
 	if (reset)
-		setbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+		setbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 	else
-		clrbits_le32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+		clrbits32(&bcr->bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 
 	return 0;
 }
diff --git a/src/soc/qualcomm/qcs405/gpio.c b/src/soc/qualcomm/qcs405/gpio.c
index fc58fae7ff..19027c32bb 100644
--- a/src/soc/qualcomm/qcs405/gpio.c
+++ b/src/soc/qualcomm/qcs405/gpio.c
@@ -78,9 +78,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
 	gpio_configure(gpio, GPIO_FUNC_GPIO,
 				pull, GPIO_2MA, GPIO_DISABLE);
 
-	clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
+	clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
 		GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT);
-	clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
+	clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
 		<< GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE
 		<< GPIO_INTR_RAW_STATUS_EN_SHIFT);
 }
diff --git a/src/soc/qualcomm/qcs405/include/soc/iomap.h b/src/soc/qualcomm/qcs405/include/soc/iomap.h
index 2ed3e10f76..7d948ec46e 100644
--- a/src/soc/qualcomm/qcs405/include/soc/iomap.h
+++ b/src/soc/qualcomm/qcs405/include/soc/iomap.h
@@ -48,8 +48,8 @@
  */
 #define readl_i(a)           read32((const void *)(a))
 #define writel_i(v, a)       write32((void *)a, v)
-#define clrsetbits_le32_i(addr, clear, set)  \
-	clrsetbits_le32(((void *)(addr)), (clear), (set))
+#define clrsetbits32_i(addr, clear, set)  \
+	clrsetbits32(((void *)(addr)), (clear), (set))
 
 #define GCC_CLK_CTL_REG			((void *)0x01800000u)
 #define MSM_CLK_CTL_BASE		GCC_CLK_CTL_REG
diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c
index 827448ce91..f621778f65 100644
--- a/src/soc/qualcomm/qcs405/spi.c
+++ b/src/soc/qualcomm/qcs405/spi.c
@@ -247,10 +247,10 @@ static void write_force_cs(const struct spi_slave *slave, int assert)
 {
 	struct qcs_spi_slave *ds = to_qcs_spi(slave);
 	if (assert)
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_EN);
 	else
-		clrsetbits_le32(ds->regs->io_control,
+		clrsetbits32(ds->regs->io_control,
 			SPI_IO_CTRL_FORCE_CS_MSK, SPI_IO_CTRL_FORCE_CS_DIS);
 }
 
@@ -275,7 +275,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds)
 	 * Configure Mini core to SPI core with Input Output enabled,
 	 * SPI master, N = 8 bits
 	 */
-	clrsetbits_le32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
+	clrsetbits32(ds->regs->qup_config, QUP_CONFIG_MINI_CORE_MSK |
 						QUP_CONF_INPUT_MSK |
 						QUP_CONF_OUTPUT_MSK |
 						QUP_CONF_N_MASK,
@@ -288,7 +288,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds)
 	 * Configure Input first SPI protocol,
 	 * SPI master mode and no loopback
 	 */
-	clrsetbits_le32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
+	clrsetbits32(ds->regs->spi_config, SPI_CONFIG_LOOP_BACK_MSK |
 						SPI_CONFIG_NO_SLAVE_OPER_MSK,
 						SPI_CONFIG_NO_LOOP_BACK |
 						SPI_CONFIG_NO_SLAVE_OPER);
@@ -308,7 +308,7 @@ static int spi_hw_init(struct qcs_spi_slave *ds)
 	 * INPUT_MODE = Block Mode
 	 * OUTPUT MODE = Block Mode
 	 */
-	clrsetbits_le32(ds->regs->qup_io_modes,
+	clrsetbits32(ds->regs->qup_io_modes,
 				QUP_IO_MODES_OUTPUT_BIT_SHIFT_MSK |
 				QUP_IO_MODES_INPUT_MODE_MSK |
 				QUP_IO_MODES_OUTPUT_MODE_MSK,
@@ -433,18 +433,18 @@ static void enable_io_config(struct qcs_spi_slave *ds,
 {
 
 	if (write_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_OUTPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_OUTPUT_MSK, QUP_CONF_NO_OUTPUT);
 	}
 
 	if (read_cnt) {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_INPUT_ENA);
 	} else {
-		clrsetbits_le32(ds->regs->qup_config,
+		clrsetbits32(ds->regs->qup_config,
 				QUP_CONF_INPUT_MSK, QUP_CONF_NO_INPUT);
 	}
 }
diff --git a/src/soc/qualcomm/qcs405/usb.c b/src/soc/qualcomm/qcs405/usb.c
index a94973ff2b..7ddfaa231e 100644
--- a/src/soc/qualcomm/qcs405/usb.c
+++ b/src/soc/qualcomm/qcs405/usb.c
@@ -183,16 +183,16 @@ static void hs_usb_phy_init(struct usb_dwc3_cfg *dwc3)
 static void setup_dwc3(struct usb_dwc3 *dwc3)
 {
 	/* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
-	clrsetbits_le32(&dwc3->usb3pipectl,
+	clrsetbits32(&dwc3->usb3pipectl,
 		DWC3_GUSB3PIPECTL_DELAYP1TRANS,
 		DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
 
-	clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
 			DWC3_GCTL_DISSCRAMBLE),
 			DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
 
 	/* configure controller in Host mode */
-	clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
 			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
 	printk(BIOS_INFO, "Configure USB in Host mode\n");
 }
@@ -213,10 +213,10 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 
 	if (port == HSUSB_SS_PORT_0) {
 		/* Set PHY reset. */
-		setbits_le32(&dwc3->usb2_phy_bcr, BIT(1));
+		setbits32(&dwc3->usb2_phy_bcr, BIT(1));
 		udelay(15);
 		/* Clear PHY reset. */
-		clrbits_le32(&dwc3->usb2_phy_bcr, BIT(1));
+		clrbits32(&dwc3->usb2_phy_bcr, BIT(1));
 	} else {
 		clock_reset_bcr(dwc3->usb2_phy_bcr, 1);
 		udelay(15);
@@ -229,13 +229,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 
 	if (port == HSUSB_SS_PORT_0) {
 		/* Set PHY POR reset. */
-		setbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));
+		setbits32(&dwc3->usb2_phy_por_bcr, BIT(0));
 		val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
 		val &= ~(0x4);
 		write8(&dwc3->usb2_phy_dig->ctrl_common0, val);
 		udelay(20);
 		/* Clear PHY POR reset. */
-		clrbits_le32(&dwc3->usb2_phy_por_bcr, BIT(0));
+		clrbits32(&dwc3->usb2_phy_por_bcr, BIT(0));
 	} else {
 		clock_reset_bcr(dwc3->usb2_phy_por_bcr, 1);
 		val = read8(&dwc3->usb2_phy_dig->ctrl_common0);
@@ -254,13 +254,13 @@ void setup_usb_host(enum usb_port port, struct usb_board_data *board_data)
 	 */
 
 	 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
-	setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
+	setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 			PIPE_UTMI_CLK_DIS);
 	udelay(2);
-	setbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
+	setbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 			PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 	udelay(3);
-	clrbits_le32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
+	clrbits32(&dwc3->usb_qscratch_reg->qscratch_cfg_reg,
 			PIPE_UTMI_CLK_DIS);
 
 	printk(BIOS_INFO, "DWC3 and PHY setup finished\n");
diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c
index 9f3b722e31..ad89f85011 100644
--- a/src/soc/qualcomm/sc7180/gpio.c
+++ b/src/soc/qualcomm/sc7180/gpio.c
@@ -13,9 +13,9 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/mmio.h>
 #include <assert.h>
 #include <delay.h>
+#include <device/mmio.h>
 #include <timer.h>
 #include <timestamp.h>
 #include <types.h>
@@ -86,9 +86,9 @@ void gpio_input_irq(gpio_t gpio, enum gpio_irq_type type, uint32_t pull)
 	gpio_configure(gpio, GPIO_FUNC_GPIO,
 			pull, GPIO_2MA, GPIO_OUTPUT_DISABLE);
 
-	clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
+	clrsetbits32(&regs->intr_cfg, GPIO_INTR_DECT_CTL_MASK <<
 		GPIO_INTR_DECT_CTL_SHIFT, type << GPIO_INTR_DECT_CTL_SHIFT);
-	clrsetbits_le32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
+	clrsetbits32(&regs->intr_cfg, GPIO_INTR_RAW_STATUS_ENABLE
 		<< GPIO_INTR_RAW_STATUS_EN_SHIFT, GPIO_INTR_RAW_STATUS_ENABLE
 					<< GPIO_INTR_RAW_STATUS_EN_SHIFT);
 }
diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c
index e55495b86e..f3b34cf68a 100644
--- a/src/soc/qualcomm/sdm845/clock.c
+++ b/src/soc/qualcomm/sdm845/clock.c
@@ -66,7 +66,7 @@ struct clock_config qspi_core_cfg[] = {
 static int clock_configure_gpll0(void)
 {
 	/* Keep existing GPLL0 configuration, in RUN mode @600Mhz. */
-	setbits_le32(&gcc->gpll0.user_ctl,
+	setbits32(&gcc->gpll0.user_ctl,
 			1 << CLK_CTL_GPLL_PLLOUT_EVEN_SHFT |
 			1 << CLK_CTL_GPLL_PLLOUT_MAIN_SHFT |
 			1 << CLK_CTL_GPLL_PLLOUT_ODD_SHFT);
@@ -76,7 +76,7 @@ static int clock_configure_gpll0(void)
 static int clock_configure_mnd(struct sdm845_clock *clk, uint32_t m, uint32_t n,
 				uint32_t d_2)
 {
-	setbits_le32(&clk->rcg.cfg,
+	setbits32(&clk->rcg.cfg,
 			RCG_MODE_DUAL_EDGE << CLK_CTL_CFG_MODE_SHFT);
 
 	write32(&clk->m, m & CLK_CTL_RCG_MND_BMSK);
@@ -110,7 +110,7 @@ static int clock_configure(struct sdm845_clock *clk,
 				clk_cfg[idx].d_2);
 
 	/* Commit config to RCG*/
-	setbits_le32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
+	setbits32(&clk->rcg.cmd, BIT(CLK_CTL_CMD_UPDATE_SHFT));
 
 	return 0;
 }
@@ -125,7 +125,7 @@ static int clock_enable_vote(void *cbcr_addr, void *vote_addr,
 {
 
 	/* Set clock vote bit */
-	setbits_le32(vote_addr, BIT(vote_bit));
+	setbits32(vote_addr, BIT(vote_bit));
 
 	/* Ensure clock is enabled */
 	while (clock_is_off(cbcr_addr))
@@ -138,7 +138,7 @@ static int clock_enable(void *cbcr_addr)
 {
 
 	/* Set clock enable bit */
-	setbits_le32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
+	setbits32(cbcr_addr, BIT(CLK_CTL_CBC_CLK_EN_SHFT));
 
 	/* Ensure clock is enabled */
 	while (clock_is_off(cbcr_addr))
@@ -169,9 +169,9 @@ int clock_reset_bcr(void *bcr_addr, bool reset)
 	struct sdm845_bcr *bcr = bcr_addr;
 
 	if (reset)
-		setbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+		setbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 	else
-		clrbits_le32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
+		clrbits32(bcr, BIT(CLK_CTL_BCR_BLK_ARES_SHFT));
 
 	return 0;
 }
diff --git a/src/soc/qualcomm/sdm845/usb.c b/src/soc/qualcomm/sdm845/usb.c
index 8e2b9119ae..56da28e44d 100644
--- a/src/soc/qualcomm/sdm845/usb.c
+++ b/src/soc/qualcomm/sdm845/usb.c
@@ -13,10 +13,10 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/mmio.h>
 #include <stdlib.h>
 #include <console/console.h>
 #include <delay.h>
+#include <device/mmio.h>
 #include <soc/usb.h>
 #include <soc/clock.h>
 #include <soc/addressmap.h>
@@ -725,7 +725,7 @@ static void qusb2_phy_set_tune_param(struct usb_dwc3_cfg *dwc3)
 	 * tune parameters.
 	 */
 	if (tune_val)
-		clrsetbits_le32(&dwc3->qusb_phy_dig->tune1,
+		clrsetbits32(&dwc3->qusb_phy_dig->tune1,
 				PORT_TUNE1_MASK, tune_val << 4);
 }
 
@@ -762,7 +762,7 @@ static void tune_phy(struct usb_dwc3_cfg *dwc3, struct usb_qusb_phy_dig *phy)
 static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3)
 {
 	/* PWR_CTRL: set the power down bit to disable the PHY */
-	setbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
+	setbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
 
 	write32(&dwc3->qusb_phy_pll->analog_controls_two,
 			QUSB2PHY_PLL_ANALOG_CONTROLS_TWO);
@@ -782,7 +782,7 @@ static void hs_qusb_phy_init(struct usb_dwc3_cfg *dwc3)
 	tune_phy(dwc3, dwc3->qusb_phy_dig);
 
 	/* PWR_CTRL1: Clear the power down bit to enable the PHY */
-	clrbits_le32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
+	clrbits32(&dwc3->qusb_phy_dig->pwr_ctrl1, POWER_DOWN);
 
 	write32(&dwc3->qusb_phy_dig->debug_ctrl2,
 				DEBUG_CTRL2_MUX_PLL_LOCK_STATUS);
@@ -848,7 +848,7 @@ static void ss_qmp_phy_init(struct usb_dwc3_cfg *dwc3)
 static void setup_dwc3(struct usb_dwc3 *dwc3)
 {
 	/* core exits U1/U2/U3 only in PHY power state P1/P2/P3 respectively */
-	clrsetbits_le32(&dwc3->usb3pipectl,
+	clrsetbits32(&dwc3->usb3pipectl,
 		DWC3_GUSB3PIPECTL_DELAYP1TRANS,
 		DWC3_GUSB3PIPECTL_UX_EXIT_IN_PX);
 
@@ -858,18 +858,18 @@ static void setup_dwc3(struct usb_dwc3 *dwc3)
 	 * 2. Set USBTRDTIM to the corresponding value
 	 * according to the UTMI+ PHY interface.
 	 */
-	clrsetbits_le32(&dwc3->usb2phycfg,
+	clrsetbits32(&dwc3->usb2phycfg,
 			(DWC3_GUSB2PHYCFG_USB2TRDTIM_MASK |
 			DWC3_GUSB2PHYCFG_PHYIF_MASK),
 			(DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 			DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT)));
 
-	clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_SCALEDOWN_MASK |
 			DWC3_GCTL_DISSCRAMBLE),
 			DWC3_GCTL_U2EXIT_LFPS | DWC3_GCTL_DSBLCLKGTNG);
 
 	/* configure controller in Host mode */
-	clrsetbits_le32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
+	clrsetbits32(&dwc3->ctl, (DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG)),
 			DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_HOST));
 	printk(BIOS_SPEW, "Configure USB in Host mode\n");
 }