diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-11 20:05:40 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-02-12 20:47:35 +0000 |
| commit | 428a682abe7a0aaf1414d6c9d4f6c862f4c2b5fe (patch) | |
| tree | 367ff16f1244526444146c363ed9badefd1f311c /src/soc/qualcomm | |
| parent | ffab5e64d185cebfbc35e3959382910ddd5ddce8 (diff) | |
soc/amd/cezanne: drop PWRS from GNVS
A copy of Picasso's include/nvs.h was added to Cezanne right before the
commit d6ccbb9d48f97dd3bbd4b947fe3bc4857216a363 that removed it for the
other mainboards and SoCs, so apply the equivalent change here as well
to keep everything in sync.
Change-Id: I76b551c05b3c3028a3afb3bc3b77df2401aed7a8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/qualcomm')
0 files changed, 0 insertions, 0 deletions