diff options
| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2019-04-24 10:12:38 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-04-29 12:18:44 +0000 |
| commit | 3391a31cf9e74fc9e40d876aa6689e98af38882d (patch) | |
| tree | c2706780db612a6a714ead61dcb14e5a6e52001d /src/soc/qualcomm | |
| parent | c126084bc53e0f74f6085f4f84b5bc387d701a4f (diff) | |
soc/intel/common: Add support to clear GPI IS & IE registers
Add support to reset the GPI Interrupt Status & Enable registers so that
the system does not experience any interrupt storm from a GPI when it
comes out of one of the sleep states.
BUG=b:130593883
BRANCH=None
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up. Ensure that the system boots fine to ChromeOS.
Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/qualcomm')
0 files changed, 0 insertions, 0 deletions