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authorTim Wawrzynczak <twawrzynczak@chromium.org>2019-07-10 09:13:55 -0600
committerMartin Roth <martinroth@google.com>2019-07-11 15:03:09 +0000
commitc5651568ea63aedc92669c5447c0c9755e726244 (patch)
tree29f7924fd05618321471199b5806a7c241387849 /src/soc/qualcomm
parenta17242577add6dfd54d1ff8d0e46958b758e3718 (diff)
mb/google/hatch: Enable/disable GPIO clock gating
Before the system enters S0ix or S3, each GPIO community will have its dynamic clock gating turned on. Upon return to S0, the dynamic clock gating will be turned back off. BUG=b:130764684 BRANCH=none TEST=Used dut-power to verify that the clock gating is enabled in S0ix and S3. Also used Store(..., Debug) statements in the ASL code to verify it was getting called. Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/qualcomm')
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