diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2014-04-30 14:09:36 -0700 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2015-01-03 04:59:10 +0100 |
| commit | f3254348a118f2d2b666fc84a31c1ceb6881bbc5 (patch) | |
| tree | 49ee2709af999dd97bae251630de11b1ce1f6596 /src/soc/qualcomm | |
| parent | 572795bf0877627e77526fe505ad6e6158093fbc (diff) | |
ipq8064: Configure storm bootblock to run
This adds necessary configuration options to enable bootblock on Storm
to read the rombase image from the SPI flash.
BUG=chrome-os-partner:27784
TEST=manual
. after this change is applied, the AP148 boots coreboot from the
Spansion SPI flash device:
coreboot-4.0 Thu May 1 14:25:34 PDT 2014 starting...
Exception handlers installed.
SF: Detected S25FL128S_256K with page size 10000, total 2000000
CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001
coreboot-4.0 Thu May 1 14:25:34 PDT 2014 booting...
Exception handlers installed.
...
Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197801
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 73d72df228e3c6154d8836b0af6d94df91c88bf4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67
Reviewed-on: http://review.coreboot.org/7995
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/qualcomm')
| -rw-r--r-- | src/soc/qualcomm/ipq806x/Kconfig | 21 |
1 files changed, 19 insertions, 2 deletions
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 09e1c1eae0..63d10191f4 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -17,11 +17,11 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x224000 + default 0x228000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x224080 + default 0x228080 config MBN_ENCAPSULATION depends on USE_BLOBS @@ -41,6 +41,15 @@ config BOOTBLOCK_BASE hex "256K bytes left for TZBSP" default 0x40600000 +config ROMSTAGE_BASE + hex + default 0x40608000 + +config RAMSTAGE_BASE + hex + default 0x4060c000 + + config STACK_TOP hex default 0x40600000 @@ -49,4 +58,12 @@ config STACK_BOTTOM hex default 0x405fc000 +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0x405e6000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00016000 + endif |