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| author | Shunqian Zheng <zhengsq@rock-chips.com> | 2016-04-21 23:53:08 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-05-09 08:41:41 +0200 |
| commit | ce60d5a1398d62fa357f4daed3d5d5f4bdfae67e (patch) | |
| tree | d5142cef9f509d537f56e316f91676ce22c645fc /src/soc/qualcomm | |
| parent | a1f82a349820e9b0b58031eb70a9a9ff744bbc95 (diff) | |
rockchip: rk3399: add functions to configure ddrc freq
This patch list four frequencies for ddr controller,
200MHz, 300MHz, 666MHz and 800MHz and configure
each freq by setting the DPLL dividers.
By default, the clk_ddrc is from DPLL and equals to DPLL,
so here we only need to set the DPLL clock.
BRANCH=none
BUG=chrome-os-partner:51537
TEST=emerge-kevin coreboot
Change-Id: Ifabe85b5dc95e3c8e3e9cbf946e12e8b06b881cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 18ec4f7d8738472fbadd60fa3c8f810f5347ffa2
Original-Change-Id: I448057542c3885068ddffa5b37d0341ee3ec04b1
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/340184
Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org>
Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/14707
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm')
0 files changed, 0 insertions, 0 deletions