summaryrefslogtreecommitdiff
path: root/src/soc/qualcomm
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-10-25 13:32:46 +0100
committerAngel Pons <th3fanbus@gmail.com>2020-11-04 22:38:56 +0000
commitfcc26f54a0dc5db0845946b20e1a03b77a8877ae (patch)
treebc57d1ea68b538a180a39571cb5f957a36c221fb /src/soc/qualcomm
parent257b00f3575ccf7853061d75fbb4f0b362a88b36 (diff)
soc/intel/broadwell/pch/acpi: Add PCIe register offsets
These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code. Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/qualcomm')
0 files changed, 0 insertions, 0 deletions