soc/qualcomm/sdm845: Add MMU support

Initialize 1st 4GB as Device Memory, except:
 * 1st page: NULL address
 * System_IMEM: Cached SRAM
 * Boot_IMEM: Cached SRAM

TEST=build

Change-Id: Ic6cf022b08bb2568fdf956cea8bad46da89236c5
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25201
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/soc/qualcomm/sdm845/mmu.c b/src/soc/qualcomm/sdm845/mmu.c
new file mode 100644
index 0000000000..12219e8817
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/mmu.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <arch/mmu.h>
+#include <arch/cache.h>
+#include <soc/mmu.h>
+#include <soc/symbols.h>
+
+void sdm845_mmu_init()
+{
+	mmu_init();
+
+	mmu_config_range((void *)(4 * KiB), ((4UL * GiB) - (4 * KiB)),
+			MA_DEV | MA_S | MA_RW);
+	mmu_config_range((void *)_ssram, _ssram_size, MA_MEM | MA_S | MA_RW);
+	mmu_config_range((void *)_bsram, _bsram_size, MA_MEM | MA_S | MA_RW);
+
+	mmu_enable();
+}