sdm845: Add USB support on cheza platform

This patch adds code to initialize two USB DWC3.0 controllers
and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to
initialize USB3.0 on the cheza mainboard.

Synopsis controller initialization and configuration sequences taken from
USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy
programming.

Includes Super speed mode support.

TEST=USB keypad and mass-storage device enumeration tested with this patch

Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>

1 files changed, 2 insertions, 0 deletions

diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
index 896ae58e5f..d099bff717 100644
--- a/src/soc/qualcomm/sdm845/Makefile.inc
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -24,6 +24,7 @@ romstage-y += timer.c
 romstage-y += gpio.c
 romstage-y += clock.c
 romstage-$(CONFIG_SDM845_QSPI) += qspi.c
+romstage-y += usb.c
 
 ################################################################################
 ramstage-y += soc.c
@@ -33,6 +34,7 @@ ramstage-y += timer.c
 ramstage-y += gpio.c
 ramstage-y += clock.c
 ramstage-$(CONFIG_SDM845_QSPI) += qspi.c
+ramstage-y += usb.c
 
 ################################################################################