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authorT Michael Turney <mturney@codeaurora.org>2018-04-24 10:21:45 -0700
committerJulius Werner <jwerner@chromium.org>2018-05-01 23:33:45 +0000
commit7978b8b725c421679d0f87128f1e6277c4edda4b (patch)
tree515378066ccb6032782d378d944ff2e2038a7c37 /src/soc/qualcomm/sdm845/Makefile.inc
parentd9105846bc550b5240ad5bcc56f12202412d6cfe (diff)
sdm845: Add Timer support
Frequency set to 19.2 MHz TEST=build Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sdm845/Makefile.inc')
-rw-r--r--src/soc/qualcomm/sdm845/Makefile.inc8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
index bb27ef3f06..9eacbf5a88 100644
--- a/src/soc/qualcomm/sdm845/Makefile.inc
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -3,24 +3,24 @@ ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y)
################################################################################
bootblock-y += bootblock.c
-bootblock-y += timer.c
bootblock-y += spi.c
bootblock-y += mmu.c
+bootblock-y += timer.c
################################################################################
-verstage-y += timer.c
verstage-y += spi.c
+verstage-y += timer.c
################################################################################
-romstage-y += timer.c
romstage-y += spi.c
romstage-y += cbmem.c
+romstage-y += timer.c
################################################################################
ramstage-y += soc.c
-ramstage-y += timer.c
ramstage-y += spi.c
ramstage-y += cbmem.c
+ramstage-y += timer.c
################################################################################