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authorShelley Chen <shchen@google.com>2020-10-06 15:50:21 -0700
committerJulius Werner <jwerner@chromium.org>2020-10-09 19:45:40 +0000
commitafaa3d0356d5a518442701875505901e5806bb61 (patch)
tree8cce286e32939b8141c917b1b1797a7f451b0fab /src/soc/qualcomm/sdm845/Kconfig
parent53a69507c4090633ec094173d7c03723bdbb4396 (diff)
trogdor: Modify DDR training to use mrc_cache
Currently, trogdor devices have a section RO_DDR_TRAINING that is used to store memory training data. Changing so that we reuse the same mrc_cache API as x86 platforms. This requires renaming RW_DDR_TRAINING to RW_MRC_CACHE and removing RO_DDR_TRAINING in the fmap table. BUG=b:150502246 BRANCH=None TEST=FW_NAME="lazor" emerge-trogdor coreboot chromeos-bootimage Make sure that first boot after flashing does memory training and next boot does not. Boot into recovery two consecutive times and make sure memory training occurs on both boots. Change-Id: I16d429119563707123d538738348c7c4985b7b52 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sdm845/Kconfig')
-rw-r--r--src/soc/qualcomm/sdm845/Kconfig2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig
index c93ec6c1bb..2b9bef3bd5 100644
--- a/src/soc/qualcomm/sdm845/Kconfig
+++ b/src/soc/qualcomm/sdm845/Kconfig
@@ -9,6 +9,7 @@ config SOC_QUALCOMM_SDM845
select GENERIC_GPIO_LIB
select ARM64_USE_ARCH_TIMER
select SOC_QUALCOMM_COMMON
+ select CACHE_MRC_SETTINGS
if SOC_QUALCOMM_SDM845
@@ -21,6 +22,7 @@ config VBOOT
select VBOOT_RETURN_FROM_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config SDM845_QSPI
bool