diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2023-08-21 16:02:57 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2023-08-22 02:28:57 +0000 |
| commit | fae1eb3e667c59df0f39725785190fca31e51fc1 (patch) | |
| tree | 1c0c6a7bc4947bb39c0473b936ac15ae7e589da9 /src/soc/qualcomm/sc7280 | |
| parent | c1386ef6128922f49f93de5690ccd130a26eecf2 (diff) | |
soc/qualcomm: Add missing newlines for logs
Change-Id: Ifd2e0043122946211aceb5ff88db0314de720fb9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77336
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7280')
| -rw-r--r-- | src/soc/qualcomm/sc7280/display/edp_ctrl.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/soc/qualcomm/sc7280/display/edp_ctrl.c b/src/soc/qualcomm/sc7280/display/edp_ctrl.c index 2b4f5618ef..469e1b6286 100644 --- a/src/soc/qualcomm/sc7280/display/edp_ctrl.c +++ b/src/soc/qualcomm/sc7280/display/edp_ctrl.c @@ -591,7 +591,7 @@ static void edp_host_train_set(uint32_t train) uint32_t data = 0; uint32_t shift = train - 1; - printk(BIOS_INFO, "train=%d", train); + printk(BIOS_INFO, "train=%d\n", train); edp_state_ctrl(SW_LINK_TRAINING_PATTERN1 << shift); while (--cnt) { @@ -1321,18 +1321,18 @@ static void edp_ctrl_link_enable(struct edp_ctrl *ctrl, mdss_clock_configure(MDSS_CLK_EDP_LINK, 0, 1, 0, 0, 0, 0); ret = mdss_clock_enable(MDSS_CLK_EDP_LINK); if (ret != 0) - printk(BIOS_ERR, "failed to enable link clk"); + printk(BIOS_ERR, "failed to enable link clk\n"); mdss_clock_configure(MDSS_CLK_EDP_LINK_INTF, 0, 1, 0, 0, 0, 0); ret = mdss_clock_enable(MDSS_CLK_EDP_LINK_INTF); if (ret != 0) - printk(BIOS_ERR, "failed to enable link intf clk"); + printk(BIOS_ERR, "failed to enable link intf clk\n"); edp_ctrl_pixel_clock_dividers(ctrl, &m, &n); mdss_clock_configure(MDSS_CLK_EDP_PIXEL, 0, 2, 0, m, n, n); ret = mdss_clock_enable(MDSS_CLK_EDP_PIXEL); if (ret != 0) - printk(BIOS_ERR, "failed to enable pixel clk"); + printk(BIOS_ERR, "failed to enable pixel clk\n"); edp_mainlink_ctrl(1); } else { |