diff options
| author | Subrata Banik <subratabanik@google.com> | 2023-07-17 13:05:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-19 13:02:09 +0000 |
| commit | 5259568bda5c21b4640887f4c5b5bf85aa355342 (patch) | |
| tree | b71caa77b88c543657af6759a60f8632417e370e /src/soc/qualcomm/sc7280/pcie.c | |
| parent | 9d783081945031db9745e7489987e07b88210f05 (diff) | |
soc/intel/alderlake: Use 1MB CBMEM console buffer with FSP debug
Patch to increase CONSOLE_CBMEM_BUFFER_SIZE to contain FSP debug serial log.
The existing implementation uses larger cbmem size irrespective of FSP debug is enabled or
not. Ideally. larger cbmem size is required only if FSP debug is enabled.
Bug=b:284124701
TEST=Able to build and boot google/marasov.
Change-Id: I9a9e660f2738813808e0dd65d2783424b49f9a5e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7280/pcie.c')
0 files changed, 0 insertions, 0 deletions