diff options
| author | Ravi Kumar Bokka <rbokka@codeaurora.org> | 2021-01-21 02:54:48 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2021-11-15 21:28:00 +0000 |
| commit | b0d48ed88bba7f3700df120bd8aeb1eadec7d1b4 (patch) | |
| tree | 7f4f6fb1f19b4406fdd2c4c6f173ffcbafcc2322 /src/soc/qualcomm/sc7280/include | |
| parent | b8b833fc6ad9eee7ac2f73af4a4e54314dd79a87 (diff) | |
sc7280: Add CPUCP firmware support
CPUCP is CPUSS Control Processor. It refers to the firmware for control
CPUSS active power management.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sc7280/include')
| -rw-r--r-- | src/soc/qualcomm/sc7280/include/soc/addressmap.h | 3 | ||||
| -rw-r--r-- | src/soc/qualcomm/sc7280/include/soc/cpucp.h | 45 |
2 files changed, 48 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7280/include/soc/addressmap.h b/src/soc/qualcomm/sc7280/include/soc/addressmap.h index 599d03f7b6..8515a048f8 100644 --- a/src/soc/qualcomm/sc7280/include/soc/addressmap.h +++ b/src/soc/qualcomm/sc7280/include/soc/addressmap.h @@ -55,4 +55,7 @@ #define QUP_WRAP1_BASE 0x00AC0000 #define QUP_1_GSI_BASE 0x00A04000 +#define EPSSTOP_EPSS_TOP 0x18598000 +#define EPSSFAST_BASE_ADDR 0x18580000 + #endif /* __SOC_QUALCOMM_SC7280_ADDRESS_MAP_H__ */ diff --git a/src/soc/qualcomm/sc7280/include/soc/cpucp.h b/src/soc/qualcomm/sc7280/include/soc/cpucp.h new file mode 100644 index 0000000000..37ae7d2b53 --- /dev/null +++ b/src/soc/qualcomm/sc7280/include/soc/cpucp.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_QUALCOMM_SC7280_CPUCP_H__ +#define _SOC_QUALCOMM_SC7280_CPUCP_H__ + +#include <soc/addressmap.h> + +struct epsstop_epss_top { + uint32_t access_override; + uint32_t global_enable; + uint32_t trace_bus_ctrl; + uint32_t debug_bus_ctrl; + uint32_t muc_hang_det_ctrl; + uint32_t muc_hang_irq_sts; + uint32_t muc_hang_count_threshold; + uint32_t muc_hang_count_sts; + uint32_t muc_hang_det_sts; + uint32_t l3_voting_en; +}; + +struct epssfast_epss_fast { + uint32_t epss_muc_clk_ctrl; + uint32_t muc_rvbar; + uint32_t muc_rvbar_ctrl; + uint32_t muc_non_secure_dmem_start_addr; + uint32_t muc_non_secure_dmem_end_addr; + uint32_t reserved_1[2]; + uint32_t cpr_data_fifo[4]; + uint32_t reserved_2[4]; + uint32_t pll_data_fifo[4]; + uint32_t reserved_3[4]; + uint32_t gfmux_data_fifo_1[4]; + uint32_t cpu_pcu_spare_irq_status; + uint32_t cpu_pcu_spare_irq_clr; + uint32_t cpu_pcu_spare_wait_event; + uint32_t seq_mem[256]; +}; + +static struct epsstop_epss_top *const epss_top = (void *)EPSSTOP_EPSS_TOP; +static struct epssfast_epss_fast *const epss_fast = (void *)EPSSFAST_BASE_ADDR; + +void cpucp_fw_load_reset(void); +void cpucp_prepare(void); + +#endif // _SOC_QUALCOMM_SC7280_CPUCP_H__ |