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| author | Kangheui Won <khwon@chromium.org> | 2021-06-25 16:03:05 +1000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-07-21 16:53:17 +0000 |
| commit | ce0fad5e39c7d5b32ea39f2bb56b1f2b26de89f8 (patch) | |
| tree | e85f5103b76cbeb69fe3617bbba2f8c2aa00508a /src/soc/qualcomm/sc7180/spi.c | |
| parent | ce291b4327a888920fad453103094630ca247a57 (diff) | |
soc/amd/cezanne: enable crypto in psp_verstage
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/soc/qualcomm/sc7180/spi.c')
0 files changed, 0 insertions, 0 deletions