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author | Felix Held <felix-coreboot@felixheld.de> | 2023-02-07 12:27:10 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2023-02-08 13:10:31 +0000 |
commit | 5bdedae900628858d6e06f546c7e0d5a67baf6df (patch) | |
tree | ddaf0c1bfb2c05987c2c3016b03aad934115388b /src/soc/qualcomm/sc7180/qclib.c | |
parent | 4e4dde484ae86602ada8a56796fc803a5a3b62ea (diff) |
soc/amd/mendocino/data_fabric: add Rembrandt DF_MMIO_REG_SET_SIZE
In contrast to Mendocino and all other AMD SoCs in the coreboot tree,
Rembrandt, on which Mendocino is based on, has a DF_MMIO_REG_SET_SIZE of
3 instead of 4, so the next data fabric MMIO register is 3 DWORDs after
the last one instead of the 4 DWORDs on the other SoCs. This was checked
against PPR #56558 Rev 3.04.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I454ad5d182f0040db93c9b3a83941333392c6061
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/soc/qualcomm/sc7180/qclib.c')
0 files changed, 0 insertions, 0 deletions