diff options
| author | Taniya Das <tdas@codeaurora.org> | 2021-06-23 08:53:39 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2021-09-03 06:03:08 +0000 |
| commit | 310edec6177445a69968a7b8c7a9a89252f58008 (patch) | |
| tree | d4c0e79f86a65725f2b31765a9c96e3adb867cbe /src/soc/qualcomm/sc7180/include | |
| parent | a74eb4f6e8ccf5a181563273b156e02633fa08b6 (diff) | |
qualcomm/sc7180: Clean up drivers with common clock
As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.
Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
The older convention in the upcoming patches would be replaced with
the common macro of QCOM_CLOCK_DIV, thus need the divider needs to
be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;
To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7180/include')
| -rw-r--r-- | src/soc/qualcomm/sc7180/include/soc/clock.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/soc/qualcomm/sc7180/include/soc/clock.h b/src/soc/qualcomm/sc7180/include/soc/clock.h index b303efefc1..bb46062e11 100644 --- a/src/soc/qualcomm/sc7180/include/soc/clock.h +++ b/src/soc/qualcomm/sc7180/include/soc/clock.h @@ -28,8 +28,6 @@ #define AOP_RESET_SHFT 0 #define RCG_MODE_DUAL_EDGE 2 -#define WDOG_RESET_BIT_MASK 1 - #define SCALE_FREQ_SHFT 11 struct sc7180_clock { @@ -298,12 +296,12 @@ static struct sc7180_disp_cc *const mdss = (void *)DISP_CC_BASE; void clock_init(void); void clock_reset_aop(void); void clock_configure_qspi(uint32_t hz); -int clock_reset_bcr(void *bcr_addr, bool reset); +void clock_reset_bcr(void *bcr_addr, bool reset); void clock_configure_qup(int qup, uint32_t hz); void clock_enable_qup(int qup); void clock_configure_dfsr(int qup); int mdss_clock_configure(enum mdss_clock clk_type, uint32_t source, - uint32_t half_divider, uint32_t m, uint32_t n, uint32_t d); + uint32_t divider, uint32_t m, uint32_t n, uint32_t d); int mdss_clock_enable(enum mdss_clock clk_type); #endif // __SOC_QUALCOMM_SC7180_CLOCK_H__ |