diff options
| author | Taniya Das <tdas@codeaurora.org> | 2021-06-23 08:53:39 +0530 |
|---|---|---|
| committer | Shelley Chen <shchen@google.com> | 2021-09-03 06:03:08 +0000 |
| commit | 310edec6177445a69968a7b8c7a9a89252f58008 (patch) | |
| tree | d4c0e79f86a65725f2b31765a9c96e3adb867cbe /src/soc/qualcomm/sc7180/display | |
| parent | a74eb4f6e8ccf5a181563273b156e02633fa08b6 (diff) | |
qualcomm/sc7180: Clean up drivers with common clock
As we move to use the common clock driver, the sc7180 clock driver,
watchdog and display drivers requires few cleanups, thus update the
impacted drivers.
Earlier the display client is expected to provide 2n divider value,
as the divider value in register is in form "2n-1".
mdss_clk_cfg.div = half_divider ? (half_divider - 1) : 0;
The older convention in the upcoming patches would be replaced with
the common macro of QCOM_CLOCK_DIV, thus need the divider needs to
be updated.
mdss_clk_cfg.div = half_divider ? QCOM_CLOCK_DIV(half_divider) : 0;
To accommodate impacting the functionality, the half_divider is taken
care in the clock driver.
BUG=b:182963902
TEST=Validated on qualcomm sc7180 development board
Change-Id: Ic334fd0d43e5b4b1e43a27d5db7665f0bc151d66
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Diffstat (limited to 'src/soc/qualcomm/sc7180/display')
| -rw-r--r-- | src/soc/qualcomm/sc7180/display/dsi_phy.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/qualcomm/sc7180/display/dsi_phy.c b/src/soc/qualcomm/sc7180/display/dsi_phy.c index db4b67cfe7..a7b04a87e1 100644 --- a/src/soc/qualcomm/sc7180/display/dsi_phy.c +++ b/src/soc/qualcomm/sc7180/display/dsi_phy.c @@ -722,7 +722,7 @@ static enum cb_err enable_dsi_clk(void) {.clk_type = MDSS_CLK_PCLK0, .clk_source = 1}, {.clk_type = MDSS_CLK_BYTE0, .clk_source = 1}, {.clk_type = MDSS_CLK_BYTE0_INTF, .clk_source = 1, - .clk_div = 2, .source_div = 2}, + .clk_div = 1, .source_div = 2}, }; for (i = 0; i < ARRAY_SIZE(clks); i++) { |